Optical through silicon vias (OTSVs) have been regarded as a promising alternative to conventional (electrical) through silicon vias (TSVs) for the next-generation electro-optic heterogeneous integration. This study systematically examines the influence of fabrication imperfections on the transmission performance in terms of incident light misalignment, via geometry variation, and sidewall roughness. The results demonstrate that over a finite range of beam widths, the insertion loss can be maintained at a relatively low level of less than −0.16 dBm, and this low-loss window broadens with increasing via diameter. Moreover, an increased diameter exhibits greater tolerance to the lateral offset, as for 10 μm, 20 μm, and 30 μm vias, the insertion loss rises to 3 dB at axis misalignments of 5 μm, 10 μm, and 15 μm, respectively. Additionally, smaller-diameter OTSVs are considerably more sensitive to sidewall slope angles than their larger-diameter counterparts. Additionally, minimizing the sidewall roughness is critical for maximizing the coupling efficiency, which suggests that the etch-passivation shift needs to be as quick as possible during the deep reactive ion etch (DRIE) process. With the proposed fabrication approach and comprehensive analysis of fabrication imperfection factors, this study provides essential insights for the development of high-performance OTSVs in advanced 3D optoelectronic integration.
This paper presents a time-domain closed-loop resistive temperature sensor architecture. The design employs a frequency-locked loop (FLL)-based oscillator as the sensing element, generating a monotonic frequency response to temperature variations. The output frequency is digitized on-chip and converted into a temperature code. Within the oscillator core, a switched-capacitor technique converts frequency to voltage for closed-loop control, reducing charging/discharging voltage swings and significantly lowering dynamic power consumption. The FLL topology enhances frequency stability, minimizes distortion, and suppresses power supply sensitivity. Fabricated in a 180 nm CMOS process with a core area of 0.12 mm2, the sensor achieves a peak-to-peak inaccuracy of +1.2 °C/−0.9 °C from −40 °C to 125 °C. Operating at 1 V, the circuit consumes only 10 μW with a resolution of 51 mK within 12 ms.
Processing-in-memory and in-memory computing (PIM/IMC) are increasingly explored to mitigate the von Neumann data-movement bottleneck that limits deep neural network (DNN) performance and energy efficiency. Progress, however, remains fragmented across device substrates, architectural prototypes, mapping and scheduling methods, compiler toolchains, and benchmarking practices, making results hard to compare and slowing deployment. This survey synthesizes developments from 2019–2025 along four coupled axes: (i) memory substrates and architectural design, (ii) mapping, partitioning, and scheduling, including learning- and graph-based strategies, (iii) compilers and end-to-end deployment flows, and (iv) benchmarking datasets, metrics, and reporting norms. Drawing on over twenty representative platforms spanning static random-access memory (SRAM) and dynamic random-access memory (DRAM), emerging non-volatile, capacitive, and photonic substrates, we clarify the trade-offs separating analog/charge-domain IMC from digital SRAM/DRAM-centric PIM, including reported peaks up to 600 TOPS/W and 1.5 TOPS/mm2. We organize mapping frameworks into a unified reference taxonomy, identify recurrent evaluation pitfalls that undermine reproducibility, and highlight persistent gaps in training support, robustness under non-idealities, and coverage of large-scale GNN workloads. Finally, we outline a five-phase roadmap from benchmark standardization to industrial validation toward compiler-integrated, GNN-informed PIM/IMC systems validated on production-scale workloads.
In MOSFETs, mobility enhancement is a key factor for improving the electrical performance and enabling their use in new applications, such as low-power, digital, and medical applications. This mobility improvement can be technically achieved by using different techniques that exploit the complex behavior of mobility (Coulomb, phonon, and surface roughness mobilities). Previous reviews have primarily focused on two main technologies: the introduction of mechanical stress and crystallographic orientation. Therefore, this review summarizes all key techniques that can enhance mobility, and each of these techniques is linked to a physical origin. Mechanical stress notably affects phonon mobility, whereas silicon thickness and channel impurities mainly affect the Coulomb mobility. Moreover, the dielectric oxide type, heat treatments, surface cleaning, ionic implantation in the oxide, and oxynitrides affect surface roughness mobility. In addition, the crystallographic orientation affects Coulomb, phonon, and surface roughness mobilities. Furthermore, the study of the series resistance engineering also affects the performance. Therefore, the simultaneous use of multiple of these techniques leads to an enhancement of the effective mobility at low, medium, and high effective electric fields, and the combined effect results in a more significant mobility increase.
Cu electroplating is one of the most expensive, complex and critical steps in fabricating through-glass vias (TGVs), which serve as the core component of 2.5D or 3D integration. This paper presents a simplified 2D via electroplating model to systematically investigate the influences of electrolyte additive, current density, and via geometry on plating performance in terms of via filling profile and Cu thickness. Under a fixed accelerator concentration of 0.1 mol/m3, plating performance for both blind- and through-vias initially improves but subsequently deteriorates with increasing suppressor concentration. Notably, the through-via filling mode dramatically transitions from super-conformal to sub-conformal, achieving a maximum throwing power (TP) of 135.74%. A gradual growth in current density from 0.1 to 0.3 amps/dm2 (ASD) leads to deteriorating plating quality for both via types, with the through-via TP dropping to 95.56%. In addition, sub-conformal filling occurs in U-shaped, V-shaped, and X-shaped blind-vias if single-sided plating is employed. However, after shifting them to a through configuration with double-sided plating, complete filling can be realized across all cases. These findings offer a theoretical foundation and practical guidance for enhancing the depositing rate and minimizing/eliminating internal void for the Cu electroplating of TGVs.
The growing dependence on third-party foundries for integrated circuit (IC) fabrication has created major security concerns because of hardware Trojan (HT) insertion risks. Traditional detection methods, including side-channel analysis and golden reference models, face limitations such as sensitivity to noise, high cost, and impracticality for large-scale deployment. This work introduces a machine learning framework for HT detection that eliminates the need for golden references. The framework automatically extracts statistical features from chip data, groups chips into clusters, and uses an internal filtering process to identify the most reliable patterns. These patterns are then used to guide a learning model that can accurately separate Trojan-infected chips from clean ones. Experimental evaluation demonstrates that the proposed method achieves high detection accuracy with zero false negatives, while remaining resilient against adversarial perturbations. These findings indicate that cluster-filtered pseudo-labeling provides a practical and scalable solution for enhancing hardware security in modern IC supply chains.
We demonstrate the fabrication of air gaps in a PECVD SiN interlayer through lateral recess by employing two consecutive plasma etch steps on an AlN/SiN/Al2O3 stack. This approach enables the preservation of sub-100 nm openings in Al2O3, offering a potential optimization for the GaN-HEMT gate stack in RF applications while retaining low gate foot dimensions. A low-power, SF6-based plasma etch is introduced, and time-dependent etch profiles reveal the formation of a skirt-like profile. The process exhibits excellent selectivity between SiN and Al2O3 etch rates. Furthermore, low-power SF6 plasma produces a small self-bias voltage, and surface fluorine contamination which can subsequently be eliminated by annealing.
Fine-pitch redistribution layers (RDLs) are key enabling technologies for fan-out wafer-level packaging (FOWLP)-based interposers used in chiplet and high-bandwidth memory (HBM) integration. In this study, a CAR-based photolithography process optimized for fine-pitch RDL fabrication was evaluated to realize 2 μm/2 μm line/space (L/S) RDL structures in an FOWLP environment. Key lithographic parameters, including exposure energy, focus offset, and thermal processing conditions, were systematically optimized to establish a stable and reproducible process window. Cross-sectional analysis confirmed the structural integrity of the electroplated RDL features formed under the optimized conditions. To assess functional feasibility, channel-level electrical simulations were performed using JEDEC-defined HBM3 signal assignments. Simulated eye diagrams indicate that the fabricated fine-pitch RDL interconnects are capable of supporting HBM3-class signal transmission with a moderate level of signal integrity. The presence of jitter and noise suggests that further optimization of RDL transmission line impedance is required. Rather than presenting a fully optimized interposer solution, this work provides an engineering-level assessment of lithographic and process constraints associated with implementing 2 μm class RDLs in FOWLP-based interposers, offering practical insight into fine-pitch RDL process window definition for advanced packaging applications. This work uniquely combines systematic CAR-based lithography optimization with cross-sectional structural validation and HBM3-class channel-level simulations to define a practical process window for 2 μm/2 μm RDLs in an FOWLP environment.
