Thermal management in flip-chip packaging architectures constitutes a fundamental reliability concern in advanced microelectronic systems, where elevated junction temperatures precipitate accelerated degradation mechanisms and catastrophic device failure. This study presents a comprehensive thermal characterization of structurally compromised flip-chip assemblies through the implementation of a coupled peridynamicdifferential algebraic equation (PD-DAE) computational framework. The employed formulation facilitates highfidelity resolution of multiscale thermal transport phenomena, encompassing both transient non-equilibrium dynamics and steady-state heat dissipation, while rigorously accounting for interfacial thermal boundary resistance and crack-induced thermal discontinuities. The results show that the interfacial thermal resistance (ITR) adjacent to the chip dominates the junction temperature: increasing R1(chip-lid interface resistance) from 0 to 2 mm2 center dot K center dot W-1 raises the maximum chip temperature from 73.8 degrees C to 83.3 degrees C, while variations in R2(lid-heat sink interface resistance) have limited influence. The transient analysis reveals distinct non-Fourier thermal wave propagation and interface-induced reflection and transmission, with the chip temperature rising from 28.8 degrees C to 72.4 degrees C within 0.3 s before stabilizing at 77.2 degrees C. Crack defects are shown to hinder vertical heat flow and cause localized overheating, increasing the junction temperature by up to 5.2 degrees C, while internal cracks within the silicon induce an additional 6 degrees C rise compared with interfacial cracks. Moreover, an optimal thermal interface material (TIM) thickness of 0.15-0.20 mm achieves the lowest junction temperature, reducing it from 83.8 degrees C to 68.3 degrees C through improved interfacial conformity. Overall, the study highlights that interfacial characteristics, crack defects, and TIM configuration jointly dictate the thermal reliability of flip-chip assemblies. The proposed peridynamic-non-Fourier framework provides a robust tool for analyzing damage-induced thermal degradation and guiding the design of next-generation microelectronic packaging with enhanced heat dissipation and reliability.
This letter proposes a novel wire-bonding-free packaging concept for sub-terahertz (sub-THz) active devices. The approach utilizes a quartz substrate with metal strips patterned on its bottom surface, termed flip-quartz, to achieve direct and broadband interconnection between the chip and planar transmission line. By eliminating traditional wire-bonding, the design significantly reduces parasitic effects and radiation losses, which are critical at sub-THz frequencies. To demonstrate the feasibility, a D-band (110-170 GHz) power amplifier (PA) module was designed, fabricated, and experimentally tested. The measured results exhibit good agreement with on-wafer measurements. Across the entire D-band, the measured small-signal gain is greater than 19 dB, the saturated output power exceeds 17 dBm, and the calculated average insertion loss remains below 1.2 dB. These results establish the proposed packaging concept as a promising solution for future sub-THz applications.
Sintered silver (Ag), as the most promising chip interconnect material for high-temperature silicon carbide (SiC) power module packaging, is often subjected to thermal stress during the packaging process and high temperature service conditions, which greatly reduce the thermal mechanical reliability of SiC power module. In this article, the prediction parameters of the interface strength of sintered Ag interconnection layer considering metallized layer and high temperature aging effects were obtained and evaluated by the method of machine learning-assisted experiments and simulations. A multilayered MLP (multilayer artificial neural network)-LSTM (long short-term memory) framework-based model was proposed, which shows higher classification and prediction ability. In this method, MLP was used to extract classification features under different metallized layers effect, and LSTM was used to extract time features for long and short-term prediction of mechanical properties degradation caused by high temperature aging. The presented multilayered MLP-LSTM method has successfully identified the relevant mechanical parameters of the cohesive zone model (CZM) directly from the load-displacement responses of die shear test. The CZM parameters related to interface bonding strength of sintered Ag interconnection layer are predicted and the mechanism of shear strength is also determined rapidly with high accuracy.
In this letter, a large chip-width terahertz monolithic integrated circuits (TMICs) packaging solution at terahertz (THz) frequencies is presented. The proposed electromagnetic bandgap (EBG) structure in this design can effectively suppress various interference modes generated when the slit width increases. The mode conversion and interconnection between coplanar waveguide with ground (CPWG) and waveguide are realized using integrated on-chip dipole antenna transition model. To verify the proposed solution, a packaging structure accommodating a chip width of 3760 $\mu $ m and an on-chip integrated dipole antenna transition model were designed and fabricated. The test results show that in the frequency range of 214-242 GHz, the return loss is better than 9 dB and the insertion loss is better than 4 dB, the de-embedded average loss is less than 1 dB.
Silver paste is widely used in power electronics as a die-attach material owing to its low-temperature sinterability, high melting point, and excellent electrical and thermal conductivities in sintered joints. However, owing to the mismatch in the coefficient of thermal expansion (CTE) between the joints and chip, the high Young’s modulus of sintered silver hinders the mitigation of the high thermal stress generated during the operation of power modules, which increases the susceptibility of sintered joints to cracking, thereby leading to potential failure. This study developed a facile approach to synthesizing bayberry-like Ag microparticles (AgMPs) through the in situ assembly of silver nanorods, resulting in a uniform distribution of nanoscale structures and mesopores on the particle surface. These particles exhibited a high specific surface area of 2.5389 m2·g−1, which enhanced their sintering activity, enabling sintering to occur at 149.7 °C. Furthermore, the porous structure of the AgMPs effectively reduced the density of joints formed by sintering AgMP paste, thereby lowering the Young’s modulus of the joints. The small grain size and intricate internal substructure of the joints yielded high shear strength, which reached 112.50 MPa at 250 °C. The Young’s modulus could be adjusted, and the pores provided by the AgMPs maintained the Young’s modulus within a low range (15.11–29.61 GPa), effectively mitigating thermal stress. These new bayberry-like porous AgMPs offer a promising option for die-attach materials in electronic packaging.
