Thermal management in flip-chip packaging architectures constitutes a fundamental reliability concern in advanced microelectronic systems, where elevated junction temperatures precipitate accelerated degradation mechanisms and catastrophic device failure. This study presents a comprehensive thermal characterization of structurally compromised flip-chip assemblies through the implementation of a coupled peridynamicdifferential algebraic equation (PD-DAE) computational framework. The employed formulation facilitates highfidelity resolution of multiscale thermal transport phenomena, encompassing both transient non-equilibrium dynamics and steady-state heat dissipation, while rigorously accounting for interfacial thermal boundary resistance and crack-induced thermal discontinuities. The results show that the interfacial thermal resistance (ITR) adjacent to the chip dominates the junction temperature: increasing R1(chip-lid interface resistance) from 0 to 2 mm2 center dot K center dot W-1 raises the maximum chip temperature from 73.8 degrees C to 83.3 degrees C, while variations in R2(lid-heat sink interface resistance) have limited influence. The transient analysis reveals distinct non-Fourier thermal wave propagation and interface-induced reflection and transmission, with the chip temperature rising from 28.8 degrees C to 72.4 degrees C within 0.3 s before stabilizing at 77.2 degrees C. Crack defects are shown to hinder vertical heat flow and cause localized overheating, increasing the junction temperature by up to 5.2 degrees C, while internal cracks within the silicon induce an additional 6 degrees C rise compared with interfacial cracks. Moreover, an optimal thermal interface material (TIM) thickness of 0.15-0.20 mm achieves the lowest junction temperature, reducing it from 83.8 degrees C to 68.3 degrees C through improved interfacial conformity. Overall, the study highlights that interfacial characteristics, crack defects, and TIM configuration jointly dictate the thermal reliability of flip-chip assemblies. The proposed peridynamic-non-Fourier framework provides a robust tool for analyzing damage-induced thermal degradation and guiding the design of next-generation microelectronic packaging with enhanced heat dissipation and reliability.
This letter proposes a novel wire-bonding-free packaging concept for sub-terahertz (sub-THz) active devices. The approach utilizes a quartz substrate with metal strips patterned on its bottom surface, termed flip-quartz, to achieve direct and broadband interconnection between the chip and planar transmission line. By eliminating traditional wire-bonding, the design significantly reduces parasitic effects and radiation losses, which are critical at sub-THz frequencies. To demonstrate the feasibility, a D-band (110-170 GHz) power amplifier (PA) module was designed, fabricated, and experimentally tested. The measured results exhibit good agreement with on-wafer measurements. Across the entire D-band, the measured small-signal gain is greater than 19 dB, the saturated output power exceeds 17 dBm, and the calculated average insertion loss remains below 1.2 dB. These results establish the proposed packaging concept as a promising solution for future sub-THz applications.
Sintered silver (Ag), as the most promising chip interconnect material for high-temperature silicon carbide (SiC) power module packaging, is often subjected to thermal stress during the packaging process and high temperature service conditions, which greatly reduce the thermal mechanical reliability of SiC power module. In this article, the prediction parameters of the interface strength of sintered Ag interconnection layer considering metallized layer and high temperature aging effects were obtained and evaluated by the method of machine learning-assisted experiments and simulations. A multilayered MLP (multilayer artificial neural network)-LSTM (long short-term memory) framework-based model was proposed, which shows higher classification and prediction ability. In this method, MLP was used to extract classification features under different metallized layers effect, and LSTM was used to extract time features for long and short-term prediction of mechanical properties degradation caused by high temperature aging. The presented multilayered MLP-LSTM method has successfully identified the relevant mechanical parameters of the cohesive zone model (CZM) directly from the load-displacement responses of die shear test. The CZM parameters related to interface bonding strength of sintered Ag interconnection layer are predicted and the mechanism of shear strength is also determined rapidly with high accuracy.
In this letter, a large chip-width terahertz monolithic integrated circuits (TMICs) packaging solution at terahertz (THz) frequencies is presented. The proposed electromagnetic bandgap (EBG) structure in this design can effectively suppress various interference modes generated when the slit width increases. The mode conversion and interconnection between coplanar waveguide with ground (CPWG) and waveguide are realized using integrated on-chip dipole antenna transition model. To verify the proposed solution, a packaging structure accommodating a chip width of 3760 $\mu $ m and an on-chip integrated dipole antenna transition model were designed and fabricated. The test results show that in the frequency range of 214-242 GHz, the return loss is better than 9 dB and the insertion loss is better than 4 dB, the de-embedded average loss is less than 1 dB.
Silver paste is widely used in power electronics as a die-attach material owing to its low-temperature sinterability, high melting point, and excellent electrical and thermal conductivities in sintered joints. However, owing to the mismatch in the coefficient of thermal expansion (CTE) between the joints and chip, the high Young’s modulus of sintered silver hinders the mitigation of the high thermal stress generated during the operation of power modules, which increases the susceptibility of sintered joints to cracking, thereby leading to potential failure. This study developed a facile approach to synthesizing bayberry-like Ag microparticles (AgMPs) through the in situ assembly of silver nanorods, resulting in a uniform distribution of nanoscale structures and mesopores on the particle surface. These particles exhibited a high specific surface area of 2.5389 m2·g−1, which enhanced their sintering activity, enabling sintering to occur at 149.7 °C. Furthermore, the porous structure of the AgMPs effectively reduced the density of joints formed by sintering AgMP paste, thereby lowering the Young’s modulus of the joints. The small grain size and intricate internal substructure of the joints yielded high shear strength, which reached 112.50 MPa at 250 °C. The Young’s modulus could be adjusted, and the pores provided by the AgMPs maintained the Young’s modulus within a low range (15.11–29.61 GPa), effectively mitigating thermal stress. These new bayberry-like porous AgMPs offer a promising option for die-attach materials in electronic packaging.
Development of the high-power devices based on the third-generation semiconductor puts forward a high requirement for the thermal performance of electronic packaging materials. In this study, we employed oligomeric bismaleimide (BMI), multifunctional epoxy resin (EP), and 4.4’-daminodiphenylmethane (DDM) as the resin matrix to prepare a new BMI/EP/DDM (BED) ternary resin molding compound aiming for high-temperature electronic packaging. With 2-ethyl-4-methylimidazole as the curing accelerator, the reactions including the addition of BMI with DDM, addition of EP with DDM, self-polymerization of EP, and self-polymerization of BMI facilely occurred during the curing process of BED system, making the molding process of BED be compatible with that of commercial epoxy molding compounds (EMC). With increasing the BMI content, the thermal stability of the cured BED resins was improved, showing the initial thermal decomposition temperature and char yield at 800 °C up to 388 °C and 55.7
The high-temperature applications of Silicon Carbide (SiC) power devices are constrained by traditional epoxy molding compound (EMC). A significant challenge arises from the mismatch between the thermal expansion coefficients (CTE) of the encapsulant and the SiC chip, generating thermal and mechanical stresses during prolonged high-temperature operation. While glass encapsulants offer stability above 300 degrees C, these stresses can lead to mechanical degradation and eventual failure of SiC power devices. We design a glass-based encapsulation material to adjust the CTE of the glass to match that of the SiC chip (3-9 ppm/degrees C), enabling encapsulation of the device for long-term operation at 300 degrees C. Finite element analysis (FEA) confirms that the CTE adjustment effectively reducs internal thermal stresses. The glass composite with 10 wt% PbTiO3 3 demonstrates a Tg g of 310 degrees C and a CTE of 8.48 ppm/degrees C, successfully encapsulating a SiC schottky barrier diode in TO-247 package form. The encapsulated device exhibits low leakage current, a reverse breakdown voltage of 1,700 V, and a thermal resistance of 0.45 degrees C/W. Notably, the device maintains excellent performance even after 1,176 h of high- temperature aging, including 336 h at 300 degrees C and exhibits minimal change during thermal cycling between-50 and 150 degrees C for 100 cycles. Long-term performance analysis demonstrates superior stability compared to EMC encapsulation. These results highlight the potential of glass-based encapsulants for wide band gap power devices, offering reliability and performance under extreme conditions.
In this article, a novel ultrawide wire-bonding and vertical via interconnection are proposed for 3-D system in package (SiP) by embedded nonuniform elliptic technique. The vertical compensation structure of the bonding wires is constructed by an elliptic capacitive stripline with a series inductance short via. For vertical via interconnection, the elliptical slot is employed to act as a seventh-order low-pass filter with the quasi-coaxial structure, which is formed by the signal hole surrounded by several grounded holes. The impedance fluctuation is significantly reduced by gradually changing the width of the elliptic structure. The coupling between the adjacent wires is added to build the equivalent circuit model, which can accurately analyze the transmission behavior of the wire-bonding interconnection. From the measurement results, the return loss is better than 15 dB and the insertion loss is less than 1 dB within the frequency range of dc-43.5 GHz.
Due to excellent thermal conductivity, high aspect ratio, and low density, mesophase pitch -based carbon fibers (MPCFs) are highly desired in electronic packaging. However, their thermal conductivity is hard to present in the polymer matrix because of the disordered stacking and low filling. Moreover, few researches are focused on the enhancement of the electrical insulation performance for MPCFs. Herein, we report vertically aligned and insulating boron nitride (BN) coated carbon fiber (CF) powders as significant fillers for polymer composites, endowing markedly improved thermal conductivity and electrical insulation. The high -quality BN coating layer on the surface of the CF is produced by a cooling precipitation method and high -temperature treatment with ingenious use of solubility properties, exhibiting a conformal, dense, and highly crystalline structure. This preparation method overcomes the limitations of coating thickness and particle agglomeration, resulting in a 31fold enhancement of the electrical resistivity of the CF powders. After orientation treatment in a silicone rubber matrix, such CF@BN-filled pads exhibit good thermal conductivity, significantly improved insulation performance, and excellent mechanical properties. Among them, the optimized pad achieves a thermal conductivity of 12.06 W m -1 K -1 , a volume resistivity of 50 x 10 8 Omega cm and a breakdown voltage of 3100 V mm -1 , exceptional flexibility, and a favorable compression ratio (@45 psi) of 41.7 %. This work provides unique insights into constructing carbon fiber fillers as well as the preparation of high thermal conductivity composites, thereby expanding the application scenarios of carbon fiber powder in electronic packaging.
The contact interface of precision mechanical equipment, such as electronic equipment, is the crucial medium for transferring internal loads and physical properties and realizing the intended function of the equipment. The thermal contact performance of precision mechanical equipment determines its overall thermal performance. Previous studies have consistently ignored the activeness of differential distribution of contact interface material stiffness in improving thermal contact performance. Therefore, this paper creatively proposed a new idea to improve thermal contact performance by designing the material stiffness of the contact interface. Firstly, based on the precise analysis model of thermal contact performance considering surface roughness, a heuristic-based optimization design method of material stiffness of contact interface was developed, which took the contact interface temperature distribution non-uniformity (CITDN) and thermal contact resistance (TCR) as the optimization objectives. Then, based on this method, the optimization designs of electronic chip packaging and proton exchange membrane fuel cell (PEMFC) were carried out. The results showed that after optimization, the TCR and CITDN of the electronic chip package were reduced by 83.23% and 92%, respectively, and the TCR and CITDN of PEMFC were decreased by 99.78% and 88.71%, respectively. This method achieved a substantial improvement in thermal contact performance.
Flip chip technology has been used extensively in microelectronic packaging due to the high density, fine spacing, smaller size. However, the size and spacing of the solder bumps are decreasing gradually, defect detection is getting more and more difficult. Thus, the growing demand for high reliability has generated considerable attention on the importance of defect inspection. This paper proposes an in-situ infrared thermography monitoring method with in situ monitoring system bases on modified thermal resistance network model that added the phase transition for the non-destructive analysis of packaging process. The different defects, such as missing bump and pad, missing bump, and bridge are inspected with an accuracy of up to 90 % based on in situ monitoring system. The maximum error between the model and the experiment is 27.6 %, while the minimum error is 13.6 %. The experiment results show that the max temperature of missing bump and pad, missing bump is 35.43 °C and 6.13 °C higher than normal, and the bridge is 0.44 °C lower than normal, respectively. The maximum amplitude by the Fourier transform is used to inspect due to the max temperature of normal and bridge are indiscernible, the results show that the bridge is 4 lower than normal. The model and experimental results show that the in-situ infrared thermography monitoring method is effective for detecting defects in high density electronic devices. The proposed method of in situ monitoring is expected to provide a new strategy for next generation of three-dimensional heterogeneous integrated chips defect inspection.
Gallium Oxide (Ga2O3) holds significant potential for the next generation of electronic devices following SiC and GaN due to its ultra-wide bandgap of approximately 4.5 eV - 4.9 eV and high theoretical critical breakdown field strength of 8 MV/cm. Nonetheless, Ga2O3 has a naturally low thermal conductivity, resulting in limited device output performance and hindering Ga2O3 devices from reaching their full theoretical potential. In this study, we demonstrate that the appropriate thermal management strategy can solve the above challenges. By comparing the thermal control schemes including the Ga2O3 FET devices on the original substrate, the thinned Ga2O3 substrate, the high thermal conductivity substrate, the heat sink packaging, and the flip-chip packaging, it is demonstrated that the flip-chip model is the most effective strategy to improve the heat dissipation performance of the Ga2O3 device. By utilizing the appropriate carrier in flip-chip packaging, the temperature elevation of the device at 2 W/mm power density will be diminished by around 91% in contrast to the initial basic device. Furthermore, the output performance of the device demonstrates significant enhancement. This thermal management technique successfully resolves the severe heat dissipation issue prevalent in Ga2O3 devices and eliminates primary obstacles concerning the industrialization of Ga2O3 RF and power devices.
柔性有机发光二极管(OLED)因使用柔性衬底而对环境中的水氧更加敏感,这对封装技术提出了更高的要求.目前,柔性OLED封装技术中最具希望的发展方向是可柔性化、水氧隔离能力优异的薄膜封装(TFE)技术.TFE是在OLED表面制备一层或者多层超薄的薄膜材料,以阻隔水氧侵蚀的封装技术,其关键在于制备水氧隔离能力优异的薄膜并避免对OLED器件性能产生影响.介绍了柔性OLED的衬底选择和传统的刚性封装技术,阐明了 TFE的优势,通过无机/有机薄膜的制备及TFE采用的在线封装和离线封装2种方法,对柔性TFE的发展现状进行了总结,并对柔性TFE的发展做出了展望.
从室外环境、净化厂房环境和深紫外光刻机设备内部的微环境3个层面,梳理空气颗粒污染物、空气分子污染物和振动等工艺环境问题的来源,构建深紫外光刻工艺环境模型.分析准分子激光器、光路、上版系统、传片系统和主工作台等深紫外光刻机主要部件在工艺环境控制方面的特殊要求.研究深紫外光刻工艺使用的化学放大光刻胶的工作机理,分析空气分子污染物对光刻胶乃至整个光刻工艺的影响.研究空气颗粒污染物、空气分子污染物和振动有关的技术标准和控制等级要求.提炼、总结深紫外光刻工艺环境控制方案,逐级开展空气颗粒污染物控制、空气分子污染物控制、温湿度控制和防微振工作.
随着半导体工艺的发展,芯片工艺提升愈发困难,摩尔定律日趋放缓,而芯粒集成技术促进了多芯片封装的发展,有效地延续了摩尔定律.以2.5D、3D集成为主的芯粒异构集成芯片的测试方法与传统2D芯片测试有所不同,带来一些新的测试挑战.从当前芯粒测试的挑战分析入手,介绍了芯粒互联标准、互联测试和基于不同测试访问标准的可测性设计(DFT)方法,着重阐述各方法的优缺点以及相互之间的联系与区别,旨在帮助读者对芯粒测试技术进行系统性了解.
低温共烧陶瓷(LTCC)封装散热通孔设计是集成电路封装设计的重要内容之一.以某CLCC40型LTCC外壳为例,使用有限元仿真软件对几种不同的散热通孔设计进行3D建模和稳态热仿真.通过对比芯片结到外壳的热阻仿真结果,得到了散热通孔的优化设计方案.仿真结果表明,采用该设计的LTCC外壳的散热效果优于质量分数为92％的氧化铝陶瓷外壳,但略差于氮化铝陶瓷外壳.
GaN作为第三代半导体材料的代表,具有优越的电学性能,被应用在诸多领域.随着功率密度提升、工作频率增加,GaN器件会产生明显的热效应,温度对GaN的性能及可靠性有直接影响,因此热阻测试及结温表征是非常重要的.根据GaN器件的结构、工作原理以及特性参数,结合JEDEC热阻测试的标准,对不同电压等级、不同封装结构的GaN器件进行测试,验证了使用导通电阻作为温度敏感参数的热阻测试方法的正确性.
大数据时代对高速总线的高带宽、低延时及高灵活性有更苛刻的要求,高速串行总线(PCIe)与FPGA的集成能够满足新兴领域的需求,但需要对其在高温和低温下的性能稳定性及低功耗性进行探究.以16nm FinFET工艺SRAM型FPGA为对象,搭建针对低功耗PCIe第三代(Gen3)的高速通信的性能测试、温升测试以及高温及低温功耗测试方案.测试结果表明,在通信过程中被测电路与CPU通信稳定,读、写速率分别可达3 907 MB/s、4 430 MB/s,达到理论最大带宽的54.1％、61.4％;被测电路温升不显著,常温下电路的表面温度比对照电路低18.4％;其在高温125 ℃下的功耗比对照电路低41.9％.该工艺下的电路能够稳定运行PCIeGen3总线,并在低功耗、低发热状态下实现高质量的信号传输.
随着NAND Flash在存储器市场中的占比与日俱增,对NAND Flash的测试需求也越来越大.针对NAND Flash存储器中存在的故障类型进行讨论,并对现有测试算法进行分析,为提高故障覆盖率以及降低测试时间,对现有的March-like测试算法做出改进,改进算法比March-like算法的故障覆盖率提高了 16.7％,测试时间减少了 30％.完成存储器内建自测试(MBIST)电路设计,设计了FPGA最小系统板并进行板级验证,结果验证了 MBIST电路以及改进的测试算法的可行性.
随着智能电网、新能源发电技术和轨道交通的发展,中压和高压电力电子设备是必然的发展趋势,因此需要越来越多的高压功率半导体模块来降低拓扑和控制系统的复杂性.在应用时,单芯片高压SiC MOSFET与串联低压SiC MOSFET相互竞争.前者由于工艺不成熟,成本较高;后者由于器件串联,寄生电感较大.与技术不成熟且昂贵的高压SiC芯片相比,通过串联低压SiC器件来实现高阻断电压更具成本效益.低压SiC器件的串联方式包括模块级串联和芯片级串联,目前芯片级串联器件的研究还很少.
