Acquisition of ultrasound standard views is a prerequisite for performing ultrasound diagnosis. With the aim of solving the clinical imaging challenge that adult liver standard sections have long been constrained by physicians' subjective experience, this paper collects 12 common liver ultrasound standard sections from the Second Hospital of Fujian Medical University and investigates and discusses the adaptability of the Vision-Transformer(ViT)-based deep learning automatic recognition method in liver ultrasound standard sections. Using a regional pixel set segmentation operation on liver ultrasound images, we found that the ViT model achieved recognition accuracy of 92.9% in the available ultrasound dataset when the basic segmentation module was 16*16 and the depth was 12. We also compared other mainstream deep learning frameworks based on convolutional neural networks, and the ViT model outperformed all other methods, guided by the features of the visual attention mechanism. The work in this paper provides a rich research base for deep learning of liver ultrasound based on the visual attention mechanism, and to a certain extent standardises the medical examination of the liver in adults by ultrasound-based means.
Complex software programs place higher demands on processors' floating-point performance. As a promising and open-source Instruction Set Architecture (ISA), RISC-V can be extended to meet a wide range of requirements. In this paper, we design a tightly-coupled Floating-Point Unit (FPU) based on a RISC-V processor SweRV EH1 core. This FPU supports RV32F instruction set. Both simulation and FPGA prototype were built to verify it. It ran 4.5x faster than the original core, with a Whetstone benchmark score of 1.13 MWIPS/MHz. We also did logic synthesis using TSMC 90nm process library. It shows that the whole design can run at a maximum frequency of 350 MHz, and the area of this FPU is about 27.5 kGE.
For a multi-core system with multiple peripherals, the usual communication between cores and data transmission between cores and peripherals is single, and the data transfer cannot be planned, shaped, or congested-controlled. In this research, a Data Navigator that is used to manage data transport in a multi-core system is studied. The Data Navigator consists of two parts: Data Manager and Data Transfer Controller. When so many devices are requested to transmit data, the data manager uses a three-level priority adjustment technique, and the data transfer controller switches to DMA mode and uses the AXI bus to convey the data. The proposed architecture may provide equitable and efficient data transmission in a certain multi-core system environment, balance response speed, complete data shaping, and improve system performance overall, according to experimental results.
This paper presents a fast sensing front-end integrated circuit for nanopore-based DNA sequencing. Single-stranded DNA passes through the nanopore on the cell membrane to generate an ultra-small current on the electrodes. Therefore, a trans-impedance amplifier and a voltage-to-time conversion circuit are designed and optimized in this work to realize the current detection. This front-end IC reduces the single base detection time to $\mathbf{10}\ \boldsymbol{\mu}\mathbf{s}$ at minimum. The whole circuit is implemented in 180-nm CMOS process. The results show that the implemented IC can detect the minimum current of 10 pA and can measure the current through nanopores ranging from 10 pA to 150 pA. Its power consumption is $\mathbf{42}.\mathbf{8}\ \boldsymbol{\mu}\mathbf{W}$ , and the input reference noise of the input stage is 1.93 pV 2 /Hz.
The multi-view stereo reconstruction method based on deep learning is usually affected by the weak-textured area or occlusion in the real scene. Therefore we propose a multi-view stereo reconstruction network method with a hybrid attention mechanism. A hybrid attention module is added to the feature extractor to improve the performance in weak-textured regions. In order to reduce occlusion effects a module is used to adjust the view weights. We find adding depth-adaptive partitioning will improve the performance of our method. Our method is trained and tested on the DTU and Tanks and Temples datasets, the results show that our method has good results in terms of reconstruction accuracy and completeness.
Due to the universal coverage of the 5 th Generation (5G) mobile communication networks, indoor positioning based on 5G radio signal has attracted significant research and industrial interests. Accurate signal propagation models are beneficial to 5G communications and high precision 5G positioning. However, in the sub-6GHz frequency band of 5G networks, the traditional plane wave-front and spherical wave-front signal models are no longer fully applicable for indoor environments. In this paper, we propose a mixed wave-front signal model by combining the plane wave-front signal model with the spherical wave-front signal model. Simulation results show that when applied with the classic Space-Alternating Generalized Expectation-maximization (SAGE) algorithm, the proposed mixed model can yield better results in channel parameter estimation.
The determination of circuit type is an important prerequisite for automatic design of analog circuits. However, the same type of circuit will have some variants due to different design requirements or designers. In this paper, a graph convolution network framework used for analog circuit classification is proposed, which can effectively identify circuits and their variants. First, we convert the analog circuit netlist into the data of graph structure, and the circuit information is represented by features. By converting the data of graph structure into Fourier domain, we can convolute the circuit graph and propagate it linearly, and extract the characteristics of the circuit to identify the circuit type. We performed experiments on the data set of analog circuits, and the experimental results showed that the proposed graph convolutional network based method achieved the promising performance in identifying types of circuits and their variants.
This paper proposes a channel Resource Allocation (RA) scheme based on location information for Vehicle-to-Vehicle (V2V) communications. The fast time-varying character of the wireless channel makes the channel resource allocation of V2V communications a challenging problem. However, the wireless channel, between the transmitter and the receiver depends on their locations, which are slowly changing. It is better to take the location information into consideration for the channel allocation scheme of V2V. Therefore, we propose a novel location-based RA scheme to maximize the system energy efficiency of both Cellular User Equipments (CUEs) and Vehicular User Equipments (VUEs). Simulation results show that the algorithm effectively improves the energy efficiency of CUEs and VUEs, reducing the algorithm's computational complexity in a large number of user scenarios.
With the continuous improvement of processor performance requirements, technologies such as superscalar, deep pipeline, and multi-core which can improve instruction parallelism are frequently used. Under this technical background, branch prediction errors will increase the delay used to flush the pipeline and greatly reduce the performance of the processor. Therefore, for high-performance processors, branch predictors with high prediction accuracy are particularly important. Based on the open source RISC-V processor core SweRV EH1, this paper adopts two prediction predictors, the hybrid predictor, and the TAGE predictor to improve the prediction performance of the original processor. This paper uses the riscv-tests self-checking test scheme to verify the instruction set of the optimized processor and completes the prototype verification on the Kintex-7 KC705 FPGA. Based on PowerStone and CoreMark test programs, this paper separately evaluates the branch prediction performance and processor performance of the processor core with two kinds of branch predictors. Experiments show that the implementation of the hybrid predictor and the TAGE predictor respectively improves the branch prediction accuracy of PowerStone programs by 3.65% and 3.39%; the average branch prediction rate respectively reaches 85.98% and 90.06%. The performance of SweRV EH1 is respectively improved by 2.56% and 5.43%.
SM2 algorithm is widely used in financial IC cards. It has the advantages of fast operation speed and short signature, but it may also contain security vulnerabilities. Attackers can crack the secret key via Simple Power Analysis (SPA), which is the inexpensive and extremely effective method, causing a great threat to the security of SM2 algorithm. In order to improve the safety of SM2 algorithm, this paper introduces atomic algorithm to implement point addition and point doubling operation, and proposes precomputed Non Adjacent Form (NAF) random window algorithm to achieve scalar multiplication. Based on experimental analysis with SAKURA-G FPGA board, the improved SM2 algorithm can resist successfully SPA. Compared with the original algorithm, the time of computation is reduced by 67.5%, and the number of slice registers has increased by less than 5%. The security and speed of SM2 algorithm has been significantly improved.
In recent years, with the globalization of semiconductor processing and manufacturing, integrated circuits have gradually become vulnerable to malicious attackers. In order to detect Hardware Trojans (HTs) hidden in integrated circuits, it has become one of the hottest issues in the field of hardware security. In this paper, we propose to apply Principal Component Analysis (PCA) and Support Vector Machine (SVM) to hardware Trojan detection, using PCA algorithm to extract features from small differences in side channel information, and then obtain the principal components. The SVM detection model is optimized by means of cross-validation and logarithmic interval. Finally, it is determined whether the original circuit contains a hardware Trojan. In the experiment, we use the SAKURA-G FPGA board, Agilent oscilloscope, and ISE simulation software to complete the experimental work. The test results of five different HTs show that the average True Positive Rate (TPR) of the proposed method for HTs can reach 99.48%, along with an average True Negative Rate (TNR) of 99.2%, and an average detection time of 9.66s.
Relationships were discussed in this work between discharge current and electrode moving speed, ionization coefficient, field strength, gas pressure, temperature, humidity and other factors. Gas flow distribution around electrode, according to Bernoulli's law in aerodynamics, was analyzed during the electrode moving toward the target. Mechanism was explained on forming of local part low vacuum in the discharge gap. Two sub-processes of gas ionization avalanche process and surface electronic emission process were used to describe small gap discharge. With Paschen's law, analysis of influence was performed on discharge current by electrode moving speed toward the target. Experiments were conducted many times based on test platform of electrostatic discharge electrode moving speed effect, while experiment data were recorded. Long Short-Term Memory network (LSTM) model was used to train and learn experimental data, predicted peak value of discharge current at different electrode moving speeds and rise time. The experimental results show that there is a strong correlation between the electrode moving speed and the peak discharge current, while there is a certain correlation between the electrode moving speed and the current rise time, but it is relatively weak. The research results maybe have some reference significance for the proposal and formulation of non-contact electrostatic discharge standards.
Smart applications such as robot and advanced driver assistance have significantly made our life easier and better. For the sake of various constraints such as real time, many of these applications involve computing inmobile edge devices. These devices are usually powered by batteries that require energy efficient computingto enable longer interval between the charging of batteries. On the other hand, new semiconductortechnology (such as non-volatile memories, cryogenic microelectronics) and new computing paradigm (suchas in-memory computing and neural network computing) have been actively researched to support energyefficient computing.Under this background, this talk introduces its related on-going research works. In terms of applications, wehave focused on the area of robot and smart vehicles. In terms of circuit/semiconductor technologies, wehave focused on RRAM, cryogenic CMOS, near/sub-threshold low voltage circuit designs. In terms ofcomputing paradigm, we have focused on SRAM-based in-memory computing and FPGA acceleration ofneural networks. We have also built an FPGA research platform and a smart vehicle research platform. Theyenable us to interact these above topicsand perform interdisciplinary research and prototyping.
Nowdays, CNN models become more and more popular in lots of fields due to its high performance. Unfortuna-tely, the complexity of the model increases along with accuracy, which limited its applications in some fields. Until now, a lot of researches are focused on some shallow networks such as Alexnet, VGG16. The state of art models in computer vision has over one hundred layers using ResNet structure. Besides, the power consumption of the model and latency of inference also leads to the difficulties to use AI models in reality. To solve the problem, we proposed an accelerator structure to apply yolov5 model to FPGA boards. Two types of parallelisms and pipeline structure are applied. Besides, to eliminate the time of loading and saving to off-chip buffer, ping-pong buffer are used. We improve the pipeline performance by rescheduling the mac operation. Eventually, we test the performance of accelerator on ZC702. So it can be easily implemented on some resource-limited boards. The acc-elerator can speed up the inference 6 times than CPU, 17.4 times than ARM CPU on ZC702. And the throughput of single DSP outperforms the previous works.
Ultrasound images can be acquired in real-time and quickly, and also have the advantage of being low cost and no radiation. Currently, ultrasound is widely used in clinical diagnosis. With the development of ultrasound, it is slowly becoming an essential part of the imaging examinations in obstetrics. Fetal cranial ultrasound plays a vital role in assessing fetal growth and development, decreasing the rate of birth defects, monitoring pregnancy, and assessing clinical diagnosis. Due to its ability to visualize the internal structures of the fetal cranial brain in standard planes, fetal cranial ultrasound is also essential in screening for fetal structural abnormalities. However, the conventional approach relies primarily on the ultrasound doctor to do the work manually, which is a time-consuming and laborious process. This paper proposed a convolutional neural network, FCB-Net, for recognition of the ultrasound standard plane of the fetal cranial brain. There are 5361 fetal intracranial ultrasound images collected, and they were randomly divided into 4258 for model training and 1103 for testing the performance of the model. The experiments have shown that our proposed FCB-Net has the best recognition performance for the fetal cranial brain, and the accuracy of FCB-Net has reached 91.66%.
This paper proposes a UART communication interface based on APB bus with asynchronous FIFO buffer. Based on this design, the UART controller can be flexibly configured through the AMBA bus to support baud rate modification, transmission bits, configurability of parity mode and other functions. And the asynchronous FIFO buffer function is added for communication between high-speed devices and low-speed UART devices. During data transmission, the FIFO can buffer the data and the situation that the UART device occupies the APB bus and the processor for a long time can be avoided, improving the data transmission efficiency. The design is based on the UART transmission protocol. the finite state machine method is used to control the the transmission timing of UART interface, and RTL simulation and FPGA verification are carried out, showing good flexibility of this design.
In recent years, deep reinforcement learning has combined the advantages of reinforcement learning and deep learning, and has made great progress in decision-making tasks. However, the training of deep reinforcement learning requires frequent interactions between the agent and the environment and repeated experiments. Adversaries have chances to poison the sample data collected by the agent by attacking the experimental environment in the training process, thereby bringing security risks and serious consequences to the training process of reinforcement learning. This work is committed to addressing the security risks in the field of deep reinforcement learning. However, this work improves the algorithm from the perspective of sample data filtering, and improves the security performance of deep reinforcement learning algorithm. There are two contributions in this work: one is to defend against adversarial attacks against deep reinforcement learning through cluster analysis and sample value evaluation; the other is to propose a deep reinforcement learning algorithm based on sample value evaluation on the basis of deterministic strategy gradient algorithm. The algorithm uses the clustering method to classify the sample pool, and measures the contribution value and security risk of the sample to the model training through the sample value evaluation. The classic game experiments show that the proposed algorithm is safe and effective. It reduces the threat of the agent falling into the adversarial sample attack and improves the training performance of deep reinforcement learning.
LTE Vehicle-to-Vehicle (V2V) communication has emerged as a promising solution to meet the stringent requirements of automotive communication. In this paper, we propose a joint spectrum resource allocation and power control algorithm to maximize the system data rates of both Cellular User Equipment (CUE) and Vehicular User Equipment (VUE). Besides, the reliability requirements of CUEs and VUEs as well as the delay requirements of VUEs are guaranteed. Firstly, we propose a joint resource allocation optimal problem followed by transforming the optimal problem into two subproblems, i.e., the spectrum resource allocation subproblem and the power control subproblem. Secondly, we transform the spectrum resource allocation subproblem into a maximum weight matching problem for bipartite graphs. Then convex optimization and linear programming are applied to adjust the transmit power of users to further improve the system data rates. Finally, the effectiveness of the proposed algorithm is verified by the simulation results.
A QSPI interface is proposed for accessing QSPI flash in this paper. This proposed QSPI interface transmission information for the master supports access to 3 types of flash by using the Bit-decoding algorithm, that is, the data is received from MSB to LSB in order into the master. This QSPI interface includes SPI mode, DSPI mode and QSPI mode. The SPI mode has 4 clock modes to switch, for receiving and transmitting the information. The DSPI mode and QSPI mode is utilized when needed for high-speed access to flash. Based on the QSPI transmission protocol, a finite state machine is used in this QSPI interface design, which to control the transmission timing. The design is verified through RTL simulation. The simulation result shows the correct functions and transports stable data.
The loss of altitude position information of defects might result in serious over detections in the transparent plate inspection, and reduce the efficiency of the Automatic Optical Inspection (AOI). This paper proposes a layer resolved defects inspection method which uses two cameras to capture a pair of images of the defects. These two images are fused into one fusion image. A Convolution Neural Network (CNN) is trained to classify the surface where the defect is located. Then an Intersection-over-Union (IoU) based algorithm is designed to distinguish the defects for transparent plate with more than 2 surfaces. The experimental results validate the feasibility of this approach with an accuracy of 97.1% and an average detection speed of 37.45ms per defect, which is extremely helpful for industrial applications.
