In emerging blockchain-based IoT systems, highly flexible and energy-efficient hash function hardware design is necessary to maintain the operation of diverse blockchain networks. Accordingly, a coarse-grained reconfigurable array (CGRA) is the most optimal architecture for implementing hash functions; however, current CGRA-based works still have slow speeds and low energy efficiency. To solve these problems, this paper proposes a Coarse-Grained Linear Array (CGLA), upgrading from the CGRA, to perform multiple hash functions with high speed and energy efficiency. To achieve that goal, three main ideas are proposed: a self-updating data method, an expandable processing element array (PEA), and an efficient arithmetic logic unit (ALU) dedicated to hash functions. Our CGLA has been successfully implemented on a TySOM-3A FPGA. Evaluations on 45nm ASICs show that the CGLA is 2.8-8.7 times more power efficient than GPUs, and 1.3-17.8 times and 1.9-44.5 times better in throughput and energy efficiency than previous CGRAs.
This paper proposes a 3D-IC design for AI-Vision SoCs to address the limitations of performance and functionality inherent in using traditional 2D-ICs within a limited form factor. We defined criteria for subsystem partitioning focused on performance, power, and area (PPA) and implemented a 3D-IC with an efficient subsystem top and bottom die layout. The implementation results show a significant reduction in die area to approximately 59.7% of a comparable 2D-IC, including a 3D-I/O overhead of 0.285 mm 2
Implementation of deep learning models is constrained by different memory and computational requirements. While significant progress has been made in enhancing the processing element performance, the complete system throughput largely depends on memory transfer from the off-chip interfaces. This work proposes a complete on-chip solution for accelerator implementation on devices with resource constraints. We propose batch-wise clustering of the weights of DL models and in-situ generation of weights to be fed to the acceleration for the computations as per the model specifications. This architectural change is further complemented by the popular technique of zero-skipping. Experimental observations indicate that an average reduction in model parameters of more than 26% can be obtained at a 10% reduction in accuracy for three benchmark models extensively used in the literature.
Through-Silicon Vias (TSVs) are widely used as a solution to solve interconnection and power delivery issues of 3D integrated circuits. However, as manufacturing technology becomes finer, the reliability of TSVs has emerged as a significant challenge. This paper proposes a signal shifting-based reusable redundant TSV structure for infrastructure TSVs. Unlike conventional approaches where redundant TSVs left after repairs in signal-shifting structures remain unused, the proposed structure enables their utilization for repairing infrastructure TSVs. By ensuring that the proposed structure does not impact signal TSVs while utilizing redundant TSVs for infrastructure TSV repairs, it significantly enhances the reliability of semiconductors.
This paper presents an SRAM-based input bit configurable pulse-train computing-in-memory (CIM) macro for edge devices. The proposed macro computes matrix-vector-multiplications (MVM) in a bit-wise manner, generating pulse trains to overcome the limited signal margin and variations occurring in analog time-domain SRAM-based CIM macros. Furthermore, the system architecture comprises an error-free dynamic OR gate discharge computation, effectively addressing the non-linearity associated with analog computation methods. It also incorporates a dual pulse counter, which enhances the throughput of the system while maintaining high energy efficiency. The prototype 4Kb pulse train SRAM CIM was implemented using 28-nm CMOS technology, achieving 226.14 TOPS/W energy efficiency and a 5.14x increase in area efficiency compared to the state-of-the-art reaching 5.782 TOPS/mm2.
