There are increasing concerns on the security of IoT devices. Due to limited OS/firmware capability and insufficient external support in IoT devices, a new security architecture becomes imminent. “Root of Trust” and “cyber resilience” strengthened with hardware are two key security measures to make IoT devices less vulnerable to cyberattacks and have ability to recover by itself after attacks. Sec...
This paper presents a fast and efficient optimization engine with multi-directional, multi-objective algorithms based on a robust transistor sizing approach to improve digital circuit performance. However, such optimization processes are highly simulator-dependent and computationally expensive tasks. There-fore, we propose developing machine learning-based reliable models considering process and operating variations to speed up the optimization procedure by running them on developed Residual Neural Network (ResNN) models instead of running expensive circuit simulations. Results on 22nm Metal Gate High-K digital cells show a reduction in delay and leakage up to 36.7% and 18.8 %, respectively improving computational efficiency by several orders.
Semiconductor systems, whether cell-phones, laptops, servers or machine learning accelerators, require an increasing number of processing units, larger caches and faster interfaces while managing cost and power dissipation. As we continue to push the transistor, interconnect and memory scaling to smaller geometries, the industry is moving quickly towards 3D heterogeneous integration for higher den...
As we are moving into a new era with data-driven applications, not only datasets need to be analyzed in a smart way (with various kinds of neural models), but also new datasets have to be generated and observed from our living environment. As a result, life quality can be enhanced and improved with better usage of natural resources. In this paper, we will introduce new types of sensors which can b...
Heterogeneous 2.SD/3DIC integration is becoming more and more popular and important since device scaling and process shrink are becoming more and more difficult and expensive. This lecture will introduce status of advanced packaging, including FOWLP (Fan-out Wafer Level Packaging). Key technologies, applications, and achievements of modern EDA tools for 2.5D/3D IC design and analysis will also be presented
