Edge large language model (LLM) decoding on heterogeneous neural processing unit (NPU)–processing-in-memory (PIM) systems demands comprehensive design space exploration (DSE) across memory organization, operator mapping, and decoding configurations. This letter presents NPEX, a trace-driven SystemC/TLM design space explorer that captures dynamic runtime interactions overlooked by static baselines. By treating execution traces as dependence templates and resolving completion timelines online via DRAM/PIM backend models, NPEX enables high-fidelity architectural comparisons under identical workloads. Unlike conventional latency-sum (LS) and ideal-overlap (IO) models that lead to suboptimal design points, NPEX successfully identifies a balanced, partitioned architecture. At the NPEX-selected point, LS overestimates latency by up to 26.2%, while IO underestimates it by up to 13.3% and overoptimistically favors an aggressive speculation length $K$ . These results highlight that reliable NPU–PIM exploration necessitates online, trace-driven simulation.
The static random access memory (SRAM)-based physical unclonable functions (PUFs) provide a lightweight hardware primitive for device authentication in embedded systems. However, their practical deployment is limited by noise-induced bit instability, which degrades response reproducibility across repeated power-up measurements. The existing reliability-enhancement methods typically rely on centralized processing, error-correcting codes, or helper data, which may introduce additional overhead or expose sensitive device-specific information. This letter presents a federated learning (FL)-based framework for improving SRAM PUF reliability through distributed bit-error correction. A lightweight multilayer perceptron model is trained collaboratively across devices to learn bit-level instability patterns while keeping raw SRAM responses local to each device. In addition to clean-response evaluation, we examine robustness under emulated noise-induced drift to assess the effect of persistent bit perturbations on correction performance. The experimental results on SRAM measurements from eight ESP32 devices show that the proposed approach reduces average BER by 46.49% in the clean setting and by 36.19% under emulated noise-induced drift, while improving response stability for downstream authentication.
To deal with the growing needs of deep neural networks (DNNs), energy efficiency techniques such as near-threshold voltage (NTV) have been deployed, promising to reduce energy consumption by decreasing the supply voltage of accelerators. Despite its potential, the systematic application of NTV in digital compute-in-memory (DCIM) and the interplay between voltage scaling, performance, power, and reliability at the DNN level remain underexplored. In this work, we propose a system-level design framework for modeling, mapping, and architectural exploration of DCIM accelerators operating under NTV. We model and explore the configuration space of multivoltage-island DCIMs and integrate hardware (HW)-awareness that accounts for process variation (PV) and device-level reliability to avoid errors during computation. We evaluate in comparison to synthesized DCIMs in 22 nm, targeting CNNs and a Vision Transformer. Our results show up to $\times 3.35$ reduction in energy consumption of NTV DCIMs against equivalent standard compute-in-memory (CIM).
In industries like semi-conductors and aerospace, it is common for the design company to contract out part of the testing process to a Testing-as-a-Service (TaaS) company. In such a setup, both parties want to keep their intellectual property private (i.e. unknown to the other party): namely the design and its output traces for the designer, and the detailed correctness specifications for the tester. We demonstrate a practical way for conducting provably private TaaS using a cryptographically secure multi-party computation protocol. We do so for the common setup where the specification is in Signal Temporal Logic, and testing is done using robustness-guided falsification. Our implementation carefully separates the steps of falsification, and manages to be maximally secure, in the sense that the parties learn the absolutely minimum necessary for falsification. For up to a 100-dimensional input search space, the generation of one test takes less than 80 msec, and the overhead of the privacy-preserving protocol is less than 6x. These numbers mean that privacy-preserving TaaS is practical, thus enabling TaaS in security-sensitive industries.
Always-on human activity recognition (HAR) on wearable devices demands $\mu $ J-scale inference per sample. Differentiable weightless neural networks (DWNs) meet that budget by replacing arithmetic with lookup table (LUT) computation, and prior work reports 56–104 nJ per sample for DWN inference on FPGAs. How a deployed DWN responds to sensor-level input noise, and why, has nevertheless received little quantitative analysis. We quantify DWN robustness to Gaussian noise and sensor drift on UCI HAR across eight thermometer-encoding bit-widths ( $b \in \{10, {\dots },28\}$ ), decompose it into three mechanisms, and translate each mechanism into a sizing cue that hardware designers can read off the trained model. LUT-level noise absorption is largely invariant to both encoding bit-width and noise type. Accuracy is not: at matched rms magnitude, negative drift costs 27 versus 11 pp for positive drift. We trace this asymmetry downstream of the LUT layer, to the class-wise popcount margin.
