The CAL theorem quantifies worst-case unavailability in distributed cyber-physical systems in terms of inconsistency and latency, but does not model how individual events accumulate delay. We expose assumptions underlying CAL and derive ECAL, a per-event timing model that attributes each event’s delay to its causal timing sources, makes delay propagation across events explicit, and enables event-level timing diagnosis and what-if analysis. From ECAL, we derive an event-preserving counterpart of the CAL relation and show that CAL’s aggregate form can underestimate worst-case unavailability, revealing implicit assumptions in CAL such as static per-link inconsistency. Using ECAL to examine the broader 2023 CAL formulation, we further identify limitations in its apparent-latency decomposition and fixed-point processing-offset computation. The compositional apparent latency can differ from its trace-measured value, and the computed worst-case unavailability can underestimate the realized unavailability.
Controller Area Network (CAN) lacks built-in security, and deep-learning intrusion detection systems (IDS) are too heavy (memory, floating-point) for resource-constrained ECUs. We propose a lightweight IDS: a sliding window over raw CAN messages yields 17 statistics of identifier distribution, payload entropy, and inter-frame intervals, classified by a linear SVM. Evaluated on a public dataset with a strict chronological split (zero temporal leakage), the linear SVM achieves F1=0.9977; as the kernel is linear, the decision function collapses to 17 INT8 weights (161 bytes) with no F1 loss (0.998). On an STM32F407 MCU the firmware occupies 21.1KB flash and 4.7KB SRAM at 6% CPU, detecting attacks within 20–30 ms, giving the best accuracy–efficiency trade-off among ten classifiers and four CAN-specific IDS methods.
To overcome the programmability issue in multicore microcontrollers and to allow seamless portability of parallel programming libraries across the embedded computing continuum, in this paper we discuss the modifications required to the operating system and runtimes to support OpenMP and SYCL on microcontrollers. We compare the performance of parallel OpenMP and SYCL code on an emerging embedded kernel architecture: the fluid kernel. Experiments running on the RP2040 dual-core microcontroller using standard benchmarks achieve an average speedup of 1.64x (maximum 1.90x ) for SYCL and 1.65x (maximum 1.89x) for OpenMP compared to the equivalent single-core code. To the best of our knowledge, we present the first results of running SYCL code on microcontrollers.
This document introduces a publicly available requirements set and accompanying test suite designed to provide qualification artifacts to aid certification of the GNU Compiler Collection (GCC) MC/DC structural coverage toolchain for use in safety‑critical software development. The test suite extends existing GCC MC/DC tests to satisfy coverage-tool requirements applicable to the C programming language. These requirements are adapted from a FAA Software Verification Tools Assessment Study originally developed for the Ada language. The resulting package provides requirements, requirements‑based C verification cases, expected results, and bi‑directional traceability consistent with FAA DO‑178C and DO‑330 guidance, enabling its use as a certification aid in achieving Tool Qualification Level (TQL)‑5. The tests may be selectively applied to support structural coverage objectives for software across multiple criticality levels, from FAA Design Assurance Level (DAL)‑C through the most stringent DAL‑A.
This paper proposes a sub-vector partitioning framework that enables four families of hardware architectures for area- and delay-efficient multiplication modulo P = 3329, the core operation in the post-quantum encryption standard CRYSTALS-Kyber. Four architecture families are proposed and compared with two state-of-the-art designs as well as the built-in synthesis flows of Synopsys and Cadence (ASIC), and Xilinx (FPGA). On ASIC, the proposed architectures reduce critical-path by up to 29% and cell count by up to 25% versus the state-of-the-art; against the built-in synthesis baseline, the fastest instance achieves up to 2.8× speedup and the most area-efficient instance reduces cell count by up to 49%. On FPGA, the proposed families reduce LUT count by up to 21% versus the state-of-theart and critical-path by up to 15% versus the built-in Xilinx synthesis.
