Modern low-power VLSI architectures face increasing energy challenges due to data-intensive workloads in IoT and edge-AI systems. A data-centric power modeling approach was developed to capture switching activity, memory hierarchy behaviour, and on-chip data movement, enabling accurate estimation of energy beyond compute-only analysis. To accelerate power-performance estimation across large architectural design spaces, a unified graph-based hardware representation and a Graph Neural Network (GNN) surrogate were built to predict Power, Performance, and Area (PPA) with sign-off-level accuracy while avoiding costly full EDA simulations.Building on this foundation, this work introduces a reinforcement-learning-driven multi-objective Design Space Exploration (DSE) framework that automatically identifies Paretooptimal VLSI configurations. The GNN surrogate provides rapid PPA evaluation, and uncertainty-based pruning eliminates low-value candidates, significantly reducing the number of PrimeTime-PX simulations. A non-dominated sorting mechanism extracts the final Pareto frontier while optimizing for minimum power, reduced latency, and area constraints. Experimental evaluation on CNN, RNN, FFT, and DNN workloads shows an average 32% reduction in total power, 35% lower energy per inference, 17% latency improvement, and up to 75% fewer full simulations.
In analog and mixed-signal circuit applications, the bandgap reference (BGR) circuit generates a reliable output. However, process, voltage, and temperature fluctuations all have an impact on output performance. Capacitors, resistors, and amplifiers increase the size of power supplies. As a result, the trimmer circuit is recommended for the BGR circuit to reduce fluctuations and process extension. Temperature compensation provides better temperature coefficients by adjusting the transistor voltage aspect ratio. The final characteristic curves are corrected to avoid slope variations, and temperature adjustment is required to provide the reference current in the BGR circuit. Temperature coefficients (TC) are calculated using electron mobility, voltage drop across the transistor, and threshold voltage factors. The temperature-dependent threshold voltage generates a low dependency drain current. Temperature reparation is achieved through temperature coefficients, and gate-source voltage is generated in the BGR circuit. Monte Carlo simulation beats efficient methods for identifying process variations and mismatches. Designing cascade current mirrors in the BGR circuit reduces the channel length modulation impact while increasing the resistance value. The trimmer current reference circuit outperforms the efficient reference current 21 & micro;A at time of 110 to 150 & micro;S .
In recent ICs, the use of sub-threshold power management has become a necessity due to energy-efficiency. Level Shifters (LSs) are used to exchange signals between different voltage domains. They ensure the reliability of ICs and signal integrity. The low-power LS shown is a combination of multi-Vt, diode connected leakage aware, load balancing design, allowing for up shift or down-shifts. In this article the Performance optimization of Super Scalar level Shifter for High performance Computing Applications (SSLS) is proposed. SSLS integrates multi-Vt, and load-balancing inverter for optimization of performance metrics. The schematic structure is capable of converting voltages high into low as well. It is the design architecture that has the least silicon area. The proposed design is implemented using 55 nm-CMOS. This LS is capable of converting voltages from 0.30 V to 1.30 V with a 2.01 nW dynamic power. The LS has a propagation area of 7.660 um 2 and a delay of 90 ps.
Flexible piezoresistive sensors are becoming increasingly popular for soft robotics, wearable electronics, and structural health monitoring because of their low processing costs, mechanical versatility, and light weight. Here, we present the creation and multiphysics simulation of a flexible piezoresistive sensor using screen-printed SWCNT ink on polymer substrates. To achieve controlled film thickness and good adhesion, the experimental work focuses on creating a uniform SWCNT(Single Walled Carbon Nanotube) ink and using a scalable screen-printing process to deposit it. In addition to fabrication, a COMSOL Multiphysics model was created to examine the printed sensor's electromechanical response to tensile loading. In order to investigate displacement, von Mises stress, relative resistance variation, and electric potential distribution, the model combines modules for solid mechanics and electric currents. Under 0-50% tensile strain, the screen-printed CNT resistors exhibited highly linear resistance-strain responses (R2 = 0.998 for PI, 0.961 for PVC, and 0.968 for OHP) with the corresponding gauge factors at epsilon = 0.50 were 2.60 (PI), 0.85 (PVC), and 1.89 (OHP), consistent with the lower-mid range reported for printed CNT composites. Consistent with experimental trends, the simulation results demonstrate a linear resistance variation with strain and high gauge factor values. The electric potential plots shed light on charge transport throughout the printed film, while the stress distribution emphasizes the stability of the SWCNT film-substrate interface.
Ensuring data integrity is a crucial aspect of secure communication among interconnected smart devices. These systems typically employ FPGA, ASIC, or embedded processors as their core computational units. Due to their design constraints, such platforms operate with limited memory, computational power, and energy resources. This study provides a comprehensive evaluation of various lightweight block (64/128 parallel and serial variants), RECTANGLE (80/128), Klein, and mCrypton implemented on resource-constrained FPGA-based IoT architectures. Among these, AES remains widely adopted due to its balanced performance, offering a data throughput of approximately 17.7 bytes/s and a key scheduling throughput of 35.5 bytes/s. Conversely, PRESENT, recognized as one of the earliest ultra-lightweight ciphers, demonstrates superior energy efficiency with a minimal on-chip power consumption of around 111 mW. The comparative analysis highlights the trade-offs between power efficiency, hardware utilization, and throughput across different lightweight cryptographic implementations.
As silicon-based CMOS technology enters nanoscale territory and approaches its physical limit, one of the more significant advanced transistor technologies that have advanced beyond Moore's Law is thought to be Carbon Nanotube Field-effect Transistors (CNTFETs). Carbon nanotubes (CNT) have been recognized as a modern new technology which could tackle some of the weaknesses in CMOS without impacting performance or trustworthiness. A CNTFET Gate Diffusion Input (GDI) hybrid adder is a type of electronic circuit designed to perform addition using CNTFETs and combining the GDI technique with a hybrid CMOS logic style to achieve low power consumption and high speed. These circuits are also developed for approximate computing, which is beneficial for applications like image processing by trading off some accuracy for significant reductions in area, power, and delay. Furthermore, hundreds of nanowires may be added into its conductivity channels in order to increase current transport capabilities with lower supply voltages and thus providing a foundation for designing ultralarge scale analog/digital logic circuits on nanoscale levels.
In present work, a universal operational transconductance amplifier (OTA) based transadmittance mode (TAM) first order is presented. It provided high-paass (HP), low-pass (LP) and all-pass (AP) filter functions based on input excitation. It uses two OTAs and only one grounded energy storing element. Further, the filter parameter possesses electronic tunability through bias current of OTA. SPICE simulations are used. The input and output impedance of the proposed TAM filter are high, a property which is used to transform the circuit to a sinusoidal oscillator by using an additional energy storing element. The operation of the proposal is investigated using SPICE simulations and 180 nm CMOS technology parameters.
Conventional HEMTs and MOSFETs are unable to block current in the absence of gate voltage, leading to power inefficiency due to standby power consumption. This paper explores the analog characteristics of a novel Normally-Off Underlapped AlGaN/GaN-based Double Gate MOS-HEMT, designed to address the off-state current issue faced by traditional devices, making it well-suited for energy-efficient applications. The study investigates how variations in gate length affect parameters such as drain current (Id), transconductance, and the transconductance generation factor. The findings reveal that increasing the buffer length improves on-state current, enhancing overall device performance. Specifically, the device with a 180 nm buffer length demonstrates a 20% higher drain current than the 170 nm devices and a 38% improvement over the 160 nm devices.
In a lot of latest high-speed designs, the leakage current component which consumes power is similar or more than that of switching current or in other way dynamic component. The reports point towards that 70% or more proportion of entire power utilization is caused by the seepage of transistors. The fraction of leakage will rise as technology advances unless efficient methods are developed to control leakage. This article concentrates on optimizing circuits and designing strategies for automation to achieve this aim. The initial part of the article offers an overview of the low threshold NMOS transistors combined with NAND and NOR logic gates to achieve reduced power consumption and delays. Modified universal gates serve as essential blocks in designing this proposed adder cell. The second section of the article outlines various ways to optimize circuits for controlling the leakage current so as to achieve high speed 1-bit full adders created with. Simulations were carried out using Cadence Virtuoso with 45nm CMOS technology at 1 Volt supply voltage. Projected universal gates and one-bit adders are compared against basic NAND/NOR gates and with conventional adders for computing purposes. The projected adder designs through customized NAND/NOR logic styles attain remarkable saving in terms of sum and carry delay which is about more than 15.22 % at the cost of 8.67% average power consumption when compared by means of conventional designs.
In this article a low profile multiband multi slot with defected ground plane monopole antenna with passive circuit for GSM/WLAN/WiMAX/X bands applications has been presented. The proposed antenna has been implemented using multi slot cut with two slits added with dual U shaped inverted to each other on the patch to achieved multiband application with defected ground structure. The frequency bands covered (1.6-1.9 GHz)/1.7GHz, (2.7-3.1GHz)/2.8GHz, (4.7-4.9GHz)/4.8GHz and (6.8-8.7GHz)/7.4GHz and total area is covered 38 & times;29 & times;0.8mm(3). The proposed antenna has simulated peak gain 3.8 dBi, 4.6 dBi, 2.9 dBi and 5.7 dBi respectively and measured peak gain 3.4 dBi, 4.2 dBi, 2.7 dBi and 5.3 dBi respectively. and also VSWR achieved for simulated results are 1.4dB, 1.1dB, 1.3dB and 1.2dB and measured VSWR results are 1.6dB, 1.3dB, 1.5dB and 1.3dB. This antenna has generated more than 90% efficiency for all bands, 96% for 1.7GHz, 92% for 2.8GHz, 97% for 4.8GHz and 94% for 7.4GHz achieved efficiency. The proposed antenna presents a good agreement between simulated and measured results. The implemented antenna is more miniaturized than the exiting antennas. The proposed antenna has been transfer input impedance to the receiver port 50 Omega for normal return loss S11 act of the passive circuit devices elements.
This paper presents, a microcantilever designed using MEMS technology was considered for the development of a biosensor. This device is fabricated with Silicon substrate (600 micron thick), Silicon Oxide (bottom-1 micron and top-150 nm thick), Poly Silicon (150 nm thick) and Gold (200 nm thick) coating embedded polysilicon layers. The polysilicon coating serves as a piezoresistor, causes quantifiable deformation according to applied tensile and compression forces. The detection range of resistance between 0 Omega and 74 k Omega. It is observed that maximum resistance change is obtained for biotin adsorption concentration greater than 88 & micro;g/mL. However, resistance changes related to biotin adsorption is achieved at concentrations. With this experimental analysis the device is found suitable for use as biosensor.
Recently, much research has been done on DC converters to enhance the reliability and minimize the overall cost of the converters. This paper presents a detailed study of a multi-input DC-DC converter (MIC), focusing on its mathematical modelling, design methodology, prototype validation, and reliability assessment for low-power applications such as renewable energy systems and electric vehicles. The proposed converter is designed to operate with multiple energy sources, particularly solar and fuel cells. It uses various switching frequencies to achieve extensive control over the flow of power and output voltage. Steady-state modeling and reliability analysis are established to achieve precise design and analysis. This design ensures reduced voltage stress and a simpler circuit with fewer components, improving efficiency and reliability while achieving a higher voltage gain and an efficiency of 96.4%.
With the growing limitations of traditional CMOS technology at nanoscale dimensions, Carbon Nanotube Field Effect Transistors (CNT-FETs) have gained attention as a promising substitute, owing to their superior charge transport efficiency, structural strength, and thermal stability. This work introduces an innovative design approach for realizing a high-speed, energy-efficient full adder using CNTFET technology. The architecture incorporates a custom-developed XOR-XNOR logic unit featuring a grounded keeper technique to ensure signal integrity and robust operation. The proposed designs of CNFET based XOR-XNOR cell and full adder are simulated using HSPICE tool at 32nm CNTFET Stanford technology model and aims to minimize power consumption, delay and area of the circuit, and take advantage of the unique properties of CNTFETs. Additionally, the proposed CNTFET-XOR/XNOR cell design is subjected to process, voltage, and temperature (PVT) variations to evaluate its stability. The outcomes demonstrate that, in comparison to current state-of-the-art designs, the suggested design is more resilient. In this work, a XOR-XNOR cell is used to implement a 1-bit full adder as an application. This makes the proposed design acceptable for high-performance integrated circuits. The proposed full adder design demonstrates a significant reduction in power-delay product (PDP) in comparison to the existing CNTFET-based full adders, achieving improvements ranging from 16.71% to 81.07%.
The demand for compact, low-power systems-on-chip (SoCs) in healthcare devices has increased significantly, driven by the need for efficient human-machine interaction and longer battery life. One of the main challenges in these embedded systems is reducing power consumption without compromising performance. In this work, we propose a hybrid 1-bit GDI full adder (FA) circuit designed for energy efficiency and low power, which can be embedded to enhance the performance of healthcare and wearable devices. The circuit was simulated using Siemens EDA tools at a 0.13 & micro;m technology node. For comparative analysis, the performance metrics were used to compare the results with those of the existing adder circuit. The results demonstrate that the proposed design significantly reduces power dissipation, making it suitable for compact healthcare applications.
By linking commonplace objects to the web, the Internet of Things (IoT) has dramatically altered people's daily routines. The Internet of Things has many potential uses, but one of the most exciting is home automation, which unifies the management of all of a homeowner's electronic gadgets into a unified system. An Internet of Things (IoT) home automation system that makes use of NodeMCU and the Blynk IoT app offers a streamlined and effective way to manage household appliances from afar. The NodeMCU microcontroller board, in conjunction with the Blynk IoT software, allows users to effortlessly operate their devices from any location using their smartphone's. The designs of the system include a relay module that communicates with the household appliances, linked to the NodeMCU board. The Blynk IoT software makes it easy to connect relay modules to switches, so you can turn things on and off with the swipe of a screen. Google Home also allows customers to operate smart home equipment using voice commands. Anyone with a rudimentary understanding of electronics and programming may set up the system because of its easy setup and few necessary components. Moreover, a 4-or 6-channel relay module gives you the option to connect and operate many devices at once. With the suggested system, homeowners can easily upgrade their conventional houses into high-tech, automated havens that boost their convenience and quality of life at a price they can afford.
As silicon-based CMOS technology progresses into nanoscale territory and approaches its physical limit, one of the more significant advanced transistor technologies that has advanced beyond Moore's Law is believed to be Carbon Nanotube Field-effect Transistors (CNTFETs). Carbon nanotubes (CNT) have been identified as an innovative new technology which could address some of the weaknesses in CMOS without impacting performance or reliability. The CNTFET features a quasi-one dimensional structure, which enables its carrier to travel at ballistic speed with extremely high mobility. Furthermore, hundreds of nanowires may be added into its conductivity channels in order to increase current transport capabilities with lower supply voltages and thus providing a foundation for designing ultra-large scale analog/logic circuits on nanoscale levels. Technology based on carbon transistors has led to huge advancements in the manufacture of devices and design, however carbon-based process design kit (PDKs) that conform to the requirements of the design tools that are commercially available remain a major obstacle to the development of integrated circuits based on carbon. This article surveys research progress made with CNTFETs as well as their compact models, energy efficient adder circuits, and computing applications that pose specific problems.
This study investigates real-time process analysis in friction stir welding (FSW) of 6 mm thick 2050-T84 Al-Cu-Li alloy plates using integrated sensors and data acquisition systems. Three distinct hybrid tool pin profiles were evaluated to assess their influence on weld quality, particularly elongation. Real-time sensor feedback was used to monitor key parameters such as force, temperature, and torque, enabling the detection and correction of process deviations. Among the tools tested, the hybrid pin operating at 1400 rpm and a traverse speed of 4 mm/s yielded the highest tensile strength (404.2 MPa), elongation (7.56%), and joint efficiency (76.4%). This setup also recorded the highest total heat input of 1180 KJ/m, including 330 KJ/m at the pin and 25 KJ/m at the tip. Macro-and microstructural analysis revealed fine equiaxed grains in the stir zone and elongated grains in the thermomechanically affected zone. Scanning electron microscopy (SEM) confirmed ductile fracture features. Overall, the integration of real-time monitoring with optimized tool design significantly enhances weld quality and provides valuable insights for refining FSW process parameters.
Over the years, significant work has been done on high-integrity systems, such as those found in vehicles, satellites and planes, in order to reduce the probability that a logic fault triggers a failure in a system, hence having functional safety as a primary requirement. This work introduces the architecture and conceptual analysis of an Enhanced Dynamic Triple Modular Redundancy (DTMR) system, with emphasis on its novel hardware-level techniques for real-time fault detection, anticipatory data correction, and accurate physical isolation of chronically faulty modules. Fault-tolerant processing is necessary in safety-critical applications like aerospace, automotive, and industrial control, where permanent and transient faults undermine system reliability. Transient and permanent faults from modern semiconductor scaling impose severe reliability threats, requiring advanced fault-tolerance schemes with reasonable overheads. In contrast to traditional static TMR or architecture-level dynamic redundancy schemes, our outlined Enhanced DTMR incorporates a threshold-dependent fault counter for dynamic high-impedance (Z-state) isolation of faulty processing units. A special fault corrector actively corrects data streams from known faulty units before final voting, enhancing systemwide overall reliability and reducing recovery latency. Conceptual analysis reveals that this method achieves better fault mitigation rates with optimized hardware resource usage and low performance overhead, making it a viable option as a high-integrity, power-constrained embedded system.
This article aims to explore and compare the sensing capability of pristine MoSe2 nanosheet (NS) and platinum (Pt)-doped MoSe2 NS towards toxic carbon monoxide (CO) gas. First-principles-based calculations were performed to analyze the adsorption characteristics of CO on pristine MoSe2 (System I) and Pt-doped MoSe2 (System II), utilizing the Gaussian 09W and GaussView 6.0 software packages. Various crucial electrochemical properties, such as binding distance, adsorption energy, Mulliken charge profile, band structure, density of states (DOS), projected DOS (PDOS), electron density difference (EDD), X-Ray Diffraction (XRD) spectra, and several global sensing parameters, were evaluated. System I exhibited better adsorption ability (with an adsorption energy value of-1.981 eV), compared to System II (-0.536 eV). Moreover, System I also demonstrated slightly enhanced sensitivity (up to 99.79%) in comparison to System II (i.e., 99.56%). These results indicate that pristine MoSe2 NS would be a better choice for preparing high-performance CO gas sensor devices in future instead of incorporating foreign Pt dopant.
Quantum-Dot Cellular Automata (QCAs) are emerging as a promising alternative to traditional CMOS technology, characterized by their ultralow power consumption, high device density, and fast operation at the nanoscale. Using QCA, a crucial part of Field-Programmable Gate Arrays (FPGAs), we present a novel implementation of the ACTEL ACT 1 logic module in this work. In contrast to traditional CMOS designs, our concept aims to utilize the special advantages of QCA to enhance performance and drastically reduce power consumption. The development of an effective 2-to-1 multiplexer based on QCA majority gates, which serves as the foundation for the ACT 1 module, is a crucial component of our methodology. We successfully leveraged the unique characteristics of QCA to improve key performance metrics by using a hierarchical design approach. Our suggested architecture was designed and simulated using the QCA Designer software. Our simulation findings show that the design achieves a delay of 1.50 clock cycles, uses very little power, and occupies a small area of only 0.24 mu m(2). These findings demonstrate how the QCA-based ACT 1 module may facilitate the creation of high-performance, ultra-low-power FPGA designs that are ideal for the post-CMOS era.
