
In advanced technology nodes (e.g., 7 nm and beyond), logic synthesis suffers from a critical "proxy-physical mismatch", where optimizing logic-level proxies like And-Inverter Graph (AIG) node count and depth frequently fails to translate into physical power, performance, and area (PPA) improvements. Existing machine learning approaches primarily optimize these proxies without closed-loop physical validation, leaving substantial technology-aware implementation-level PPA headroom untapped. To bridge this gap, we propose Agentic-LS, a physically grounded neuro-symbolic logic synthesis framework. Instead of relying on structural proxies, Agentic-LS is directly driven by closed-loop Area-Delay Product (ADP) feedback via ASAP7 7 nm technology mapping. Methodologically, it synergizes Graph Neural Network (GNN)-extracted topological context with Large Language Model (LLM) reasoning to generate structure-aware priors. These priors guide a single PUCT macro tree augmented by stagnation-triggered local refinement under a shared physical-evaluation budget. A controlled prior comparison shows that a task-trained GNN slightly leads standalone Top-1 accuracy, whereas the zero-shot LLM gives the strongest low-budget search performance (32.40% vs. 29.34% ADP improvement at B = 10). An integrated penalty-propagation mechanism preserves a non-degrading incumbent under legality constraints. Comprehensive evaluations reveal that Agentic-LS systematically discovers strictly superior Pareto solutions. It achieves an average ADP reduction of 28.18% (with peak improvements up to 91.01%) against the expert resyn2 baseline on EPFL circuits, and outperforms the state-of-the-art FlowTune framework by 17.28% on VTR benchmarks. Across 26 circuits, ASAP7 mapping accounts for 70.3% of runtime at B = 50; B = 30 retains 92.8% of the full-budget QoR at 59.7% of the runtime. Ultimately, this work demonstrates that marrying LLM-guided structural priors with physically validated, dual-granularity search provides a highly efficient and safe paradigm for advanced-node EDA automation.