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    International Conference on Anti-counterfeiting, Security, and Identification

    International Conference on Anti-counterfeiting, Security, and Identification

    Conference

    年发文量

    研究主题

    论文(665)

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    1Automatic Recognition of Standard Liver Sections Based on Vision-Transformer
    Jiansong Zhang,Yongjian Chen,Peizhong Liu

    Acquisition of ultrasound standard views is a prerequisite for performing ultrasound diagnosis. With the aim of solving the clinical imaging challenge that adult liver standard sections have long been constrained by physicians' subjective experience, this paper collects 12 common liver ultrasound standard sections from the Second Hospital of Fujian Medical University and investigates and discusses the adaptability of the Vision-Transformer(ViT)-based deep learning automatic recognition method in liver ultrasound standard sections. Using a regional pixel set segmentation operation on liver ultrasound images, we found that the ViT model achieved recognition accuracy of 92.9% in the available ultrasound dataset when the basic segmentation module was 16*16 and the depth was 12. We also compared other mainstream deep learning frameworks based on convolutional neural networks, and the ViT model outperformed all other methods, guided by the features of the visual attention mechanism. The work in this paper provides a rich research base for deep learning of liver ultrasound based on the visual attention mechanism, and to a certain extent standardises the medical examination of the liver in adults by ultrasound-based means.

    2022引用:1
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    2A Floating-Point Unit Architecture Based on SweRV EH1 Core
    Zhen Lei,Fan Cai,Jianyang Zhou,Zichao Guo

    Complex software programs place higher demands on processors' floating-point performance. As a promising and open-source Instruction Set Architecture (ISA), RISC-V can be extended to meet a wide range of requirements. In this paper, we design a tightly-coupled Floating-Point Unit (FPU) based on a RISC-V processor SweRV EH1 core. This FPU supports RV32F instruction set. Both simulation and FPGA prototype were built to verify it. It ran 4.5x faster than the original core, with a Whetstone benchmark score of 1.13 MWIPS/MHz. We also did logic synthesis using TSMC 90nm process library. It shows that the whole design can run at a maximum frequency of 350 MHz, and the area of this FPU is about 27.5 kGE.

    2022引用:5
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    3Design and Implementation of Data Navigator for Heterogeneous Multi-Core System
    Hu Ge,Yukun Song,Duoli Zhang, Zhenjiao Chen, Yan Ma

    For a multi-core system with multiple peripherals, the usual communication between cores and data transmission between cores and peripherals is single, and the data transfer cannot be planned, shaped, or congested-controlled. In this research, a Data Navigator that is used to manage data transport in a multi-core system is studied. The Data Navigator consists of two parts: Data Manager and Data Transfer Controller. When so many devices are requested to transmit data, the data manager uses a three-level priority adjustment technique, and the data transfer controller switches to DMA mode and uses the AXI bus to convey the data. The proposed architecture may provide equitable and efficient data transmission in a certain multi-core system environment, balance response speed, complete data shaping, and improve system performance overall, according to experimental results.

    2022引用:1
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    4A Fast Current Sensing Front-End IC Design for Nanopore-Based DNA Sequencing
    Xu Liu,Qiumeng Fan, Xin Hu,Peiyuan Wan,Zhijie Chen

    This paper presents a fast sensing front-end integrated circuit for nanopore-based DNA sequencing. Single-stranded DNA passes through the nanopore on the cell membrane to generate an ultra-small current on the electrodes. Therefore, a trans-impedance amplifier and a voltage-to-time conversion circuit are designed and optimized in this work to realize the current detection. This front-end IC reduces the single base detection time to $\mathbf{10}\ \boldsymbol{\mu}\mathbf{s}$ at minimum. The whole circuit is implemented in 180-nm CMOS process. The results show that the implemented IC can detect the minimum current of 10 pA and can measure the current through nanopores ranging from 10 pA to 150 pA. Its power consumption is $\mathbf{42}.\mathbf{8}\ \boldsymbol{\mu}\mathbf{W}$ , and the input reference noise of the input stage is 1.93 pV 2 /Hz.

    2022引用:1
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    5Hybrid Attention Cascade Multi-View Stereo Network
    Weiqiang Liu,Rongshang Chen,Huarong Xu,Lifen Weng

    The multi-view stereo reconstruction method based on deep learning is usually affected by the weak-textured area or occlusion in the real scene. Therefore we propose a multi-view stereo reconstruction network method with a hybrid attention mechanism. A hybrid attention module is added to the feature extractor to improve the performance in weak-textured regions. In order to reduce occlusion effects a module is used to adjust the view weights. We find adding depth-adaptive partitioning will improve the performance of our method. Our method is trained and tested on the DTU and Tanks and Temples datasets, the results show that our method has good results in terms of reconstruction accuracy and completeness.

    2022
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    高被引作者

    作者引用发文
    Lin Tan4041
    Yuanyuan Zhou4041
    ChengXiang (Cheng) Zhai4041
    Shan Lu4041
    Zhenmin Li4041
    Xuanhui Wang4041
    Donghui Guo21445
    Jingxin Hong1793
    Gaoming Du13520
    David Lie971

    高产作者

    作者引用发文
    Donghui Guo21445
    Gaoming Du13520
    Xiaoyao Xie6320
    Duoli Zhang7217
    Tao Yang7715
    Liji Wu6413
    Shan He4613
    Lianfen Huang4412
    Lin Li5411
    Mingjie Zhuang3711

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