As the critical foundation for circuit operation, electronic components often lead to unpredictable economic losses and severe safety issues if their early faults are not addressed promptly and accurately. In practice, circuits are typically constructed by connecting independent functional modules in series across multiple levels. However, traditional analog circuit fault diagnosis methods target isolated functional modules, rendering them impractical for real-world applications. To address single-fault and multi-fault diagnosis in multi-level serial circuit modules, this paper proposes an SSA-optimized QCNN-IMRN serial circuit fault diagnosis method. The approach first employs the Sparrow Search Algorithm (SSA) to optimize the Dropout rate and iteration count of the fully connected layer, selecting optimal parameters. Second, it combines a multi-head attention mechanism with an improved residual neural network for the feature extraction module, proposing a novel Improved Multi-head Residual Neural Network (IMRN). This model captures long-range dependencies in data more deeply and comprehensively. Integrating this model with a Quadratic Convolutional Neural Network (QCNN) not only enables initial nonlinear feature extraction for enhanced diagnostic accuracy but also reduces the number of parameters in the residual module input, thereby shortening diagnostic time. A cascaded current monitoring circuit was selected as the validation subject. Experiments demonstrate the proposed method’s outstanding performance in fault diagnosis for current monitoring circuits, achieving a single-fault diagnosis accuracy of 97.86
Charge trapping and de-trapping phenomena are the core mechanism of Random Telegraph Noise (RTN), causing deviations in drain current amplitude over time due to the constant capture and emission processes of charges from the transistor’s channel. As the timing characteristics of oscillators, such as voltage-controlled oscillators and phase-locked loops, depend on the amplitude of the drain current, RTN impacts the stability of periodic signals by inducing variance in the length of the oscillation period (i.e., jitter). In this work, the time-domain jitter (under the concepts of absolute jitter, period jitter, and cycle-to-cycle jitter) induced by RTN in free-running and closed-loop oscillators is estimated. SPICE-level simulations demonstrate that the jitter of CMOS oscillators evolves differently depending on the arrangement of the oscillating structure and its timing behavior. The analysis is validated by straightforward analytical expressions and supported by experimental data from the literature. The relevance of this work lies in presenting a qualitative analysis of the RTN-induced jitter in CMOS oscillators for the characterization and evaluation of circuit design performance and reliability.
A critical demand for a global, standardized cyber-security knowledge database has evolved as a tool to detect and prevent cybercrime since cyberattacks are continuously growing in quantity, severity, and diversity. This has previously been attempted. The Common Vulnerabilities and Exposures (CVE) list compiles a comprehensive list of documented software and hardware vulnerabilities, creating a society dictionary of current threats. The MITRE ATT CK Framework provides threat intelligence with mitigation options for each documented attack style and defines adversary behavior. This study aims to create a model that highly corresponds with MITRE ATT CK Enterprise Matrix techniques using the language description contained in CVE data. To accomplish this, a data collection strategy is developed to generate a labelled CVE corpus of over 18 K entries. Furthermore, cutting-edge Natural Language Processing (NLP) approaches that take into consideration BERT-based models are utilized to construct accurate models. For our categorization challenge, we enhanced the SBERT technique. Additionally, we wish to build an adversarial attack-based oversampling strategy to solve the issue of a severely imbalanced dataset. We prioritized minimizing the multi-label problem’s substantial complexity when building this architecture. The One versus Rest method offers the benefit of conceptual simplicity when breaking down our multi-labelling problem into many binary classification jobs but building a separate BERT layer for contextualized embeddings for each of the 31 techniques proved unnecessary. The outcomes show that the suggested model outperforms the conventional models in terms of precision, F1 score, accuracy, and recall. The findings show that a fine-tuned suggested SBERT method yields better performance.
Smart grids impose stringent demands on substation protection systems. Traditional protection devices struggle to meet integration requirements due to inherent signal delays and high power consumption bottlenecks. Therefore, this research designs a highly integrated, scatter-driven system on chip to construct a bandgap reference source and digital control core. This core employs a design that separates the serial peripheral interface from the main control logic, ensuring flexible and efficient instruction processing. Concurrently, an integrated drive unit is developed. This unit combines the high-speed switching characteristics of current mode logic with the precise control capabilities of a segmented digital-to-analog converter, resolving the performance trade-off between speed and accuracy. Simulation results demonstrated that under power supply voltage scanning conditions down to 0.9 V, the root mean square jitter of current mode logic remained at an extremely low level of 4.5ps. Under high-load, low-temperature conditions, the error fluctuation of the digital-to-analog converter was suppressed within 1.2mV. Its output voltage error remained below 5mV, significantly lower than the 29mV error of the traditional option. Furthermore, its error exceeding rate remained stable below 20
The increasing use of commercial off-the-shelf (COTS) system-on-chips (SoCs) in space systems makes the operating-system consequences of radiation-induced soft errors a practical concern. This work applies pulsed-laser fault injection and a Linux-kernel monitoring framework to a representative COTS SoC. Across 55 valid experiments, we classify single-event upset (SEU)-only outcomes and single-event functional interrupts (SEFIs), map their spatial distribution, and analyze three representative propagation chains. The cases show how software-visible corruption can propagate through kernel memory management, scheduling, and exception handling, while the initiating microarchitectural fault location remains inferred. We further evaluate a combined hardening configuration based on the LLVM compiler infrastructure. No invalid-address SEFI was observed in the hardened sample, but scheduling and synchronization failures increased. Selective redundancy imposed modest runtime and code-size overhead. The findings provide an experimentally grounded framework for locating, interpreting, and mitigating operating-system-level soft-error manifestations.
