The automotive industry has widely adopted GPUs for In-Vehicle Infotainment (IVI) systems, which support applications ranging from navigation to graphics-intensive gaming. However, current automotive GPU virtualization solutions often lack the efficiency, flexibility, and low overhead required in vehicle cockpits. Insufficient isolation under dynamic workloads can cause performance fluctuations and delays, including in latency-sensitive tasks such as route planning. To address these limitations, we introduce CarDroid, a GPU virtualization solution for in-vehicle systems. CarDroid has three main components: (1) a lightweight container runtime that offloads graphics tasks and minimizes interference, (2) cross-OS buffer projection that shares a rendering buffer with the Android host to eliminate redundant cross-OS copies, and (3) a PMU-guided predictor for real-time resource adjustment. Across the tested workload combinations, these mechanisms reduce the arithmetic-mean interference ratio by 31.83%, with a virtualization-overhead premium of 9.19 percentage points over a GPU-passthrough baseline. CarDroid was piloted and validated on production cockpit platforms across 10 vehicle models at 9 automotive companies.
Knowing the precise memory footprint of applications is necessary to optimize their memory behavior via compiler passes. However, obtaining the memory footprint of workloads is challenging. Tracking heap allocations using Valgrind’s Massif tool provides insufficient information, as stack usage and allocations made by other images, such as library calls, cannot be tracked. As such, it becomes necessary to instrument individual memory instructions to learn the true memory usage of programs. However, instrumenting each memory instruction is infeasible since it causes programs to slow down exponentially, making instrumenting large programs practically impossible. Hence, it is only feasible to instrument memory references sparsely, leading to the challenge of estimating the whole program memory footprint from a small fraction of accesses. To that effort, we devise MemPrint , a statistical method to approximate the whole program memory footprint from sparse random memory traces. MemPrint achieves significant improvement over prior works that use sampled memory traces, achieving error rates ranging between 0.29%–21.71% while minimizing overhead from PIN.
Parameter-sharded training reduces device-memory use by storing model parameters as shards and reconstructing full parameters only before the computations that consume them. This materialization is implemented through frequent all-gathers, which can become exposed waits in each forward–backward training iteration. Hiding these waits is not only a communication-volume problem. It requires deciding where to launch each all-gather and how long the materialized full-parameter buffer should remain live. All-gather prefetching can overlap communication with earlier computation but extends buffer lifetime. Retaining a buffer after its forward-pass use can eliminate a re-gather before backward-pass reuse, but consumes transient memory headroom needed by other materialization decisions. We present Chorus , a compiler-runtime framework for transient parameter materialization in memory-constrained sharded training. Chorus addresses a limitation of local runtime policies that make decisions at hooks, module boundaries, or configuration thresholds. They can issue individual prefetches or suppress individual releases, but they do not jointly compare future all-gather opportunities, buffer lifetimes, and memory-headroom conflicts across the iteration. Chorus lowers the forward and backward passes into a whole-iteration graph that makes all-gathers, use-site waits, and releases explicit. It then builds a profile-guided block model and solves a mixed-integer scheduling problem that jointly chooses all-gather launch positions and iteration-local retention decisions under time-varying memory headroom. The selected schedule is realized by graph rewriting, which moves communication while preserving use-site waits, fuses compatible prefetch operations, and removes redundant releases and re-gathers. Cross-iteration persistent retention is finalized during warmup using measured runtime memory behavior. We implement Chorus on top of torch.compile and evaluate it on 7B to 13B dense Transformer models and one MoE model across 4 to 16 A100 GPUs. In the ZeRO-style stack, Chorus improves throughput by 1.10× over DeepCompile across the primary workloads. In the FSDP-style stack, the Chorus implementation on SimpleFSDP improves throughput by 1.14× over SimpleFSDP across the corresponding dense-model workloads. The benefits are greatest in network-constrained settings, where all-gather stalls are more exposed. Chorus stays within the configured memory budget and achieves a 1.35× compilation-time speedup over DeepCompile.
Memory disaggregation provides key-value stores larger memory capacity at low cost. Emerging compute express link (CXL) enables efficient memory disaggregation. It, however, dramatically slows down the system performance as disaggregated memory accesses are considerably slower than local memory accesses. This article presents Nemo, a near-memory accelerator architecture for CXL-based memory-disaggregated key-value stores. To address the CPU-accelerator latency, Nemo provides a set of new techniques that enable fast task dispatch, cache-conscious task offloading without CPU modifications, and versatile support of custom data types. We evaluate Nemo on the core in-memory index of RocksDB and six widely used in-memory indexing microbenchmarks under YCSB query workloads. Nemo reduces up to 91.8% of slow disaggregated memory accesses, achieves a 2.05× average speedup over the CPU-only configuration, and accelerates key-value stores by up to 4.5×.
Modern intelligent cockpits consolidate In-Vehicle Infotainment (IVI), navigation, and control-related services on shared heterogeneous hardware. This consolidation creates a resource-management problem because cockpit workloads have different controllability, safety, and performance requirements. Existing open-source cockpit-domain platforms either fix the hardware partition at design time or route IVI through para-virtualized I/O stacks that impose large rendering overheads. As a result, performance-sensitive IVI workloads cannot effectively use onboard GPUs even when safety-critical workloads do not need those resources. We present UniC, a unified cockpit-domain resource management system based on attribute-aware task placement. UniC models each workload through controllability, safety demand, and performance demand, and maps workloads to four execution environments through a piecewise assignment policy. UniC does not replace the underlying safety stack; it preserves hypervisor- and IOMMU-enforced boundaries for safety-critical workloads while avoiding over-provisioned isolation for low-safety infotainment tasks. For IVI, UniC realizes this placement through GPU passthrough, display synthesis acceleration, cross-platform application support, and optional nearby-edge rendering for passenger devices. In our prototype, UniC reduces normalized IVI virtualization overhead from 38.7% to 11.8% compared with the reproduced open-source AMD/Xen baseline, a 26.9-percentage-point reduction. UniC maintains hypervisor-level performance isolation across execution environments. Under controlled network impairment, in-vehicle edge rendering keeps on-screen response latency substantially more stable than a cloud-based alternative.
Sparse matrix-dense matrix multiplication (SpMM) is a core operation in scientific computing and deep learning. On multi-GPU platforms, its scalability is limited by communication bottlenecks. To address this, we propose DistSpMM, a co-design framework integrating data layout, pipelining, and communication strategies. DistSpMM introduces HSDMA, a lightweight algorithm that reduces communication by optimizing the dense matrix allocation. DistSpMM features a topology-aware two-stage pipeline that manages the IB/NVLink bandwidth disparity to maximize the overlap of computation and communication. Finally, DistSpMM employs an adaptive selector that uses a performance model to dynamically choose the optimal communication granularity (coarse vs. fine-grained) based on data sparsity and network tier. Experiments on diverse real-world datasets demonstrate the superior performance of our method. It achieves average speedups of 1.6 × to 2.6 × in single-node multi-GPU environments and 4.0 × to 5.1 × in multi-node multi-GPU environments over the baseline. Compared to the best state-of-the-art implementations, our method delivers up to 2.0 × speedup.
Modern HPC systems increasingly rely on tiered storage architectures with SSDs serving as a critical performance tier. However, the inherent asynchronous I/O characteristics of SSDs, including read/write bandwidth asymmetry and interference, pose significant challenges for traditional I/O schedulers. These challenges are exacerbated by the convergence of bursty HPC write workloads (e.g., checkpointing) and sustained AI read workloads (e.g., data streaming) on shared SSD infrastructure. Existing schedulers fail to adequately address these combined workloads, leading to suboptimal resource utilization. This article introduces HARMONI, a heterogeneity-aware reinforcement learning scheduler for mixed I/O in HPC storage systems. HARMONI leverages a graph neural network (GNN) to encode task-SSD dependencies and a hybrid interference predictor to adapt to hardware and I/O variations. Experimental results across diverse HPC and AI workloads demonstrate that HARMONI significantly reduces average makespan by up to 90% compared with state-of-the-art schedulers, effectively bridging the gap between evolving storage hardware and the dynamic I/O demands of modern HPC systems.
Self-modifying code (SMC) is a specialized technique that alters program execution by modifying instructions in executable memory pages during runtime. While historically employed for performance tuning, dynamic optimization, and obfuscation, both x86 and RISC-V-based processors continue to support SMC as part of their architectural flexibility. However, the same capability that enables adaptive and high-performance execution also opens the door for novel microarchitectural exploitation. In particular, SMC allows attackers to induce distinctive instruction fetch and cache behaviors, thereby enabling precise monitoring of shared microarchitectural resources such as instruction caches. In this article, we present the first in-depth security study of SMC on the latest Intel microarchitectures, including the latest hybrid CPU designs that balance performance and energy efficiency. We systematically analyze a set of x86 instructions that directly or indirectly invalidate instruction cache lines, revealing measurable timing asymmetries between cache hits and misses. Our results show that these SMC-induced timing artifacts can be leveraged to mount high-resolution cache attacks that are both stealthier and more reliable than traditional techniques. We demonstrate the power of our approach through two privacy-violating case studies: (1) recovering victim keystrokes with high accuracy in real time, and (2) performing website fingerprinting on hyper-threaded CPU cores, successfully targeting both the Google Chrome and Tor browsers. Beyond empirical results, we explore the architectural conditions that amplify SMC side effects, discuss the broader implications for multi-tenant and browser-based environments, and give an overview of possible hardware and software-level countermeasures.
The proliferation of IoT devices necessitates ubiquitous operating systems (UOS) for dynamic industrial edge scenarios, which face challenges including real-time demands and resource fragmentation. Existing virtualization methods are often too heavy or inflexible for these environments. In this article, we present UVirtio, a lightweight ubiquitous virtualization mechanism that enables efficient resource sharing across distributed edge devices. UVirtio introduces a device-profile-based virtual hardware abstraction layer that minimizes performance overhead. The system facilitates the collaboration and aggregation of edge devices, improving the throughput of sensor data by over 37.6% and enabling complex tasks such as face recognition on pooled AI accelerators. Furthermore, UVirtio implements a live migration mechanism using differential packing, achieving sub-40 millisecond downtime for dynamic resource reallocation, thus providing a scalable and agile virtualization solution for the ubiquitous computing frontier. Our work is open source at https://github.com/muliangshou/UVirtio/tree/main .
Depthwise convolution (DWC) is a key operator in efficient convolutional neural networks (CNNs). Recent models increasingly employ large-filter DWC to capture long-range dependencies, achieving accuracy competitive with that of vision transformers. Yet on GPUs, DWC remains far less efficient than its low FLOPs suggest and can become a runtime bottleneck, due to low arithmetic intensity, Tensor-Core mismatch, and inefficient memory access. To tackle these issues, we present Flash-DWC , a GPU library that makes DWC compute-efficient. Flash-DWC introduces a GEMV-based dataflow co-design that jointly optimizes data reuse, access order, layout, and workload tiling. This design increases arithmetic intensity, while preserving access contiguity and coalesced 128-byte memory accesses. Flash-DWC further transforms DWC GEMVs into compact high-density GEMMs on Tensor Cores, enabling efficient mixed-precision acceleration. In addition, matrix compression, a dual-path split-GEMM pipeline, and register-based input reuse further free on-chip resources, hide memory latency, and improve occupancy. We extend these techniques to both forward and backward propagation for efficient end-to-end training. Compared with the fastest cuDNN DWC algorithm, the GEMV-based CUDA-Core kernels and GEMM-based Tensor-Core kernels of Flash-DWC achieve 5.09× and 9.01× average speedups, respectively. In CNN training, Flash-DWC attains a 1.03×–14.18× speedup and matches PyTorch’s convergence on ImageNet-1K. By making DWC compute-efficient, Flash-DWC promotes the use of larger and more expressive filters.
Deep learning for solving partial differential equations (PDEs) has become increasingly prominent. The Fourier Neural Operator (FNO) architecture has been proven to be an efficient and high-precision method that is widely used in scientific research. However, FNO incurs significant overhead by increasing the scale and dimensionality of practical problems. The insufficient utilization of hardware resources in its key operations reduces the computational efficiency of FNO solvers in high-resolution and time-sensitive problem scenarios, and cannot provide effective solution capabilities. To address the latency induced by low computational resource utilization and large-scale data access and computation, we propose FNO-Speed, an integrated solution incorporating the multi-level parallel FNO-aware mapping and tiling GEMM optimization strategy and the custom-sized high-frequency signal filtering scheme. FNO-Speed effectively leverages the data characteristics of FNO layers and the GPU hierarchical structure to adopt a data tiling and partitioning strategy, implementing matrix multiplication based on vector outer products and operator fusion to replace convolution. It also adopts a data reorganization scheme and computation restructuring to address fragmented memory access operations and serial einsum in frequency-domain. The FNO-Speed optimization strategy enhances the utilization of device memory bandwidth and computational efficiency and achieves significant acceleration in both 2D and 3D problem scenarios while maintaining nearly identical accuracy. The model achieves up to 1.4× end-to-end training speedup, and the parallel efficiency achieves around 70% on 4 GPUs, fully demonstrating the effectiveness of the FNO-Speed optimization strategy in improving FNO performance.
DRAM-based Processing-in-Memory (PIM) addresses the “memory wall” by executing computations directly inside main memory. However, memory interleaving and virtual memory limit contiguous data size visible to PIM units, constraining PIM task granularity. Fine-grained PIM tasks incur significant offloading overhead that negates PIM performance benefits. To mitigate this, existing PIM systems drastically isolate PIM memory or disable memory interleaving. These design choices, however, decrease the CPU memory bandwidth and introduce extra data transfer, leading to an additional “system memory wall” that degrades CPU performance and must be resolved to realize PIM’s full potential. In this work, we propose GUMPIM, a PIM system that allows interleaved CPU pages and non-interleaved PIM pages to coexist in a U nitary and M alleable memory space with G uaranteed PIM page allocation. GUMPIM enables zero-copy during PIM task offloading and maintains CPU memory bandwidth while ensuring low PIM offloading overhead. First, we propose a dual-track memory management mechanism consisting of independent page allocation and address translation for CPU and PIM pages. Second, we design GUMPIM interface hardware on PIM-enabled DRAMs to provide a dynamic address mapping for the different data layouts of CPU and PIM pages. Third, we propose a PIM-assisted page migration mechanism that transparently migrates pages while preserving CPU access bandwidth, thereby enabling guaranteed and accelerated PIM page allocation. GUMPIM requires no changes to commodity DRAM standards; all hardware modifications are limited to the DRAM side, ensuring full compatibility with existing CPUs and enabling immediate deployment on current HBMx- and LPDDRx-based PIM platforms. Our results show only <0.1% performance degradation for CPU workloads on GUMPIM, in contrast to the 25.8% degradation on PIM systems with memory interleaving turned off. For PIM workloads, GUMPIM reduces memory allocation and CPU-part computation times by 2.7× and 4.93×, respectively, yielding an end-to-end 2.3× speedup over a state-of-the-art baseline system.
Virtual machine (VM) cross-cloud migration refers to the transfer of VMs between different cloud environments, enabling users to deploy their business with greater flexibility. However, VM cross-cloud migration faces many challenges in production due to the high latency and limited bandwidth of cross-cloud networks. These challenges are pronounced in disk migrations, where poor I/O performance persists and significantly constrains the migration process, even leads to migration failures. This drives the demand for VM migration drills, but existing solutions fail to effectively address it. We present Xtream, a production-level cross-cloud disk streaming migration system. By analyzing the business disk I/O patterns, we identify a macro-level locality pattern, characterized as multi- stripe disk access pattern, and develop a stripe -oriented prefetching algorithm in Xtream to improve I/O hit rate. Xtream designs a mechanism for collaborative cold and hot data migration to ensure timely responses to VM I/O requests. The evaluation demonstrates that Xtream reduces I/O latency by 88.2%, shortens cross-cloud VM startup time by 77.7%, and maintains an over 95% disk hit rate during migration, compared to the state-of-the-art streaming migration. In production, Xtream completes cross-cloud VM drills in 7–22 minutes depending on configuration, significantly reducing migration risks.
Large Language Models (LLMs) have enabled diverse AI applications. However, LLMs inference impose unprecedented computational and memory overhead, creating an inherent trade-off between latency Service Level Objectives (SLOs) and resource constraints. Serverless computing, with on-demand provisioning and pay-as-you-go billing, is becoming a promising paradigm for LLM serving. But existing solutions fail to integrate state-of-the-art inference optimizations, resulting in suboptimal GPU utilization and prolonged latency. While Prefill-Decode (PD) disaggregation combined with continuous batching has resolved such inefficiencies in traditional cloud deployments, migrating these techniques to serverless makes two challenges particularly pronounced: (1) SLO-constrained resource provisioning for independently scaling prefill and decode phase functions, and (2) function lifespan management to mitigate resource waste from continuous batching-induced prolonged instance lifespans. To tackle these issues, we propose CELLServe , an SLO-aware and cost-efficient serverless LLM serving system that pioneers integrating PD disaggregation and continuous batching into serverless platforms. CELLServe formalizes SLO-constrained joint resource provisioning as an optimization problem with a dedicated algorithm, and introduces an opportunistic instance merging strategy for decode phase functions to reclaim fragmented resources. Comprehensive evaluations on five mainstream LLMs and real-world traces show that CELLServe achieves 1.85×–1.92×higher request throughput than baselines under identical SLOs and GPU budgets, while sustaining high resource efficiency under dynamic workloads.
Profile Guided Optimization (PGO) utilizes a program’s runtime behavior to drive optimization, but its effectiveness relies heavily on profile freshness, as stale or unrepresentative profiles can limit or even negate its benefits. Extensive prior work has proposed techniques to mitigate profile staleness in offline PGO . Recent online optimizers go further by profiling the exact production binaries and immediately applying optimizations to running processes via code replacement. However, existing online binary optimizers such as OCOLOS and AOBO are limited to single-shot optimization. They fail to adapt to subsequent behavioral changes, rendering them suboptimal for long-running workloads with evolving runtime behaviors. Therefore, an online optimizer is required to automatically and continually re-profile and re-optimize long-running phase-changing applications. We present AutoCO , the first online binary-level continuous optimization system supporting multiple architectures (x86-64 and AArch64). To enable continuous adaptation to phase changes in target database workloads, AutoCO introduces a closed-loop system comprising four coordinated mechanisms: a phase monitoring mechanism that raises candidate phase-change events and a lifetime-aware trigger gate that suppresses optimization rounds unlikely to amortize their lifecycle costs; an address mapping mechanism that bridges runtime execution states with the original binary to enable iterative optimization; a code generation and injection mechanism that leverages mapped profiles to restructure the binary layout and safely redirects control flow; and an asynchronous resource reclamation mechanism that prevents memory bloat by safely reclaiming resources from obsolete code. This continuous process is supported by a modular design that facilitates portability across diverse ISAs. On MySQL, MongoDB, and PostgreSQL across x86-64 and AArch64, AutoCO achieves substantial initial performance boosts of up to 47.46% (MySQL), 43.17% (MongoDB), and 17.46% (PostgreSQL). Crucially, as workloads evolve, AutoCO continuously re-optimizes phases whose candidate events pass the lifetime-aware gate, yielding an additional adaptive speedup of 3.06%–23.01% over stale optimization.
The explosive growth of key-value (KV) cache size in large language model (LLM) inference poses a key challenge to the limited HBM of GPU. Offloading KV cache to host memory has become a prevalent mitigation method. However, the limited host DDR bandwidth, especially in multi-GPU inference scenarios, often leads to offloading bottlenecks, thereby restricting inference speed. Compute express link (CXL) offers a promising alternative to expand host memory capacity and bandwidth on demand. In this article, we present a bandwidth-oriented memory allocation mechanism, named AdaptiveKV, which is self-adaptive to CXL-enabled memory pools and KV cache offloading scales for LLM inference acceleration. Our systematic profiling of CXL-HBM memory bandwidth under GPU workloads reveals that conventional memory strategies neglect dynamic memory bandwidth fluctuations and various CXL memory characteristics, leading to suboptimal memory utilization. Motivated by these insights, AdaptiveKV implements three core designs: (1) a GPU memory conch model to guide memory allocation strategies, (2) a runtime predictor to predict optimal memory allocation ratios, and (3) a dynamic interleaving strategy to allocate memory pages across available NUMA nodes. Experimental results suggest that AdaptiveKV achieves a maximum speedup of 1.90× in LLM inference throughput compared with the state-of-the-art strategies. To further explore AdaptiveKV’s applicability boundary, we also present an FPGA-based CXL memory emulator with configurable performance, revealing that a CXL-to-DDR bandwidth ratio exceeding 8% yields at least a 5% speedup in LLM inference.
As a new abstraction to manage persistent data in non-volatile memory, Persistent Memory Objects (PMOs) hold (pointer-rich) data structures that can be shared among processes over many runs and system boots. While convenient and fast, such sharing opens up a new class of attacks that attempt to break inter-process isolation, allowing the attacker to compromise a non-vulnerable process through a different process and a shared PMO. Due to the difficulty in completely preventing or avoiding security attacks, we present PMO Checker, a comprehensive framework for detecting and recovering from them. Our framework includes various invariant checking and checkpointing schemes. We implement them on a real system with Linux kernel on a real platform with Intel Optane PMem memory. Our evaluation shows the effectiveness of the attack detection and various performance optimizations that keep the overheads low.
Microservices are widely shared in production user-facing applications. These shared microservices have various resource usage patterns when queries from different call graphs of different services access them. However, existing microservice management works fail to efficiently scale resources for them, mainly due to the lack of fine-grained scheduling of diverse queries. We therefore propose Delphinus , a runtime system that efficiently manages resources for shared microservices while ensuring the Quality-of-Service (QoS). Delphinus comprises a group-oriented query scheduler and a borrowing-based load adapter . The query scheduler identifies diverse queries, groups the containers of shared microservices, and schedules the queries into separate groups. The load adapter efficiently scales resources for shared microservices, and fully utilizes the idle containers among groups when the loads of diverse queries change. Results show that Delphinus reduces CPU and memory usage by 40.1% and 36.4% for shared microservices, respectively, compared to state-of-the-art works.
Exploiting matrix symmetry to halve memory footprint offers a substantial opportunity for accelerating memory-bound computations like Sparse Matrix-Vector Multiplication (SpMV). However, symmetric SpMV incurs data conflicts when concurrently writing the output vector. Previous approaches fail to address this issue efficiently, i.e., either are non-scalable or yield poor performance for large high-bandwidth irregular matrices. This article extends DCS-SpMV , a D ivide-and- C onquer (DC) based shared-memory implementation of S ymmetric SpMV. The key idea of DCS-SpMV is to recursively divide and reorder the matrix-induced conflict graph into independent subgraphs for parallel execution, and construct separate subgraphs to avoid data conflicts. The DC approach naturally transforms the input matrix into a low-conflict part and a high-conflict part, which motivates us to design a conflict-aware hybrid solution DCH-SpMV that executes these two parts using DCS-SpMV and the standard SpMV, respectively. We also develop a machine learning model for DCH-SpMV to predict the optimal number of DC recursions on a given matrix and architecture. In this work, we further optimize the hybrid DC implementation by reducing data conflicts before the DC preprocessing. First, we present a conflict-pruning strategy to decouple certain highly dense columns or rows from the conflict graph of a symmetric matrix. Second, we implement a heuristic to adaptively select the lower or upper triangular part of a symmetric matrix, leading to fewer data conflicts. Our optimizations not only facilitate the DC preprocessing, but also improve the performance of DCH-SpMV. We evaluate our work on both x86 and ARM multi-core CPUs using 298 symmetric sparse matrices from the SuiteSparse Matrix Collection. Our new optimizations improve the performance of previous version [ 42 ] by up to 4.89×, demonstrating significant speedup over the state-of-the-art approaches including the vendor-tuned Intel oneMKL library.
Accelerating load requests is an effective way to improve processor performance through reducing load request latency. Currently, state-of-the-art methods, including Hermes and TLP, are limited to accelerating off-chip load requests that are correctly predicted and cannot accelerate mispredicted off-chip load requests and any on-chip load requests. To overcome this limitation, we propose a new technique called Apollo that integrates TLP. The key innovation of Apollo lies in its transformation of the perceptron-based off-chip prediction paradigm, pioneered by Hermes, into a comprehensive multi-level cache miss prediction technique. The workflow of Apollo is as follows: (1) predicting whether a load request will miss the L1D or L2, and (2) performing arbitration to decide whether to issue a speculative load request and to which cache level the request is issued, and (3) issuing a speculative load request to the lower-level cache (either L2 or LLC) after arbitration for those predicted to miss the L1D or L2, while allowing the regular load request to concurrently access the cache hierarchy. If the prediction is correct, the regular load request eventually misses the L1D or L2 and waits for the speculative load request to finish. Therefore, Apollo can hide the L1D access latency for correctly predicted L1D miss load requests, and both L1D and L2 access latency for correctly predicted L2 miss load requests. To enable Apollo, we propose a lightweight L1D miss load predictor (L1MP), a lightweight L2 miss load predictor (L2MP), and an arbiter called Athena. L1MP and L2MP predict whether load requests will miss in the L1D and L2, respectively, while Athena performs arbitration to control the issuance of speculative load requests. Our evaluation using a diverse set of workloads shows that Apollo provides a geometric mean (geomean) performance improvement of 15.2% for the single-core processor, outperforming Hermes by 9.6% and TLP by 6.4%. For the multi-core processor, Apollo provides a geomean performance improvement of 18.5%, which is 16.8% higher than Hermes and 5.8% higher than TLP.
