Tensor Cores (TCs) are specialized hardware units designed for efficient matrix multiplication and are widely utilized in deep learning workloads. However, their adoption in more irregular highperformance computing (HPC) applications remains limited. This paper presents a methodology for effectively integrating TCs into a representative HPC application: molecular docking with AutoDockGPU. The irregular computational patterns and strict accuracy requirements of this application pose significant challenges for TC utilization. To address these, we adopt a twofold strategy: (i) accelerating sum reduction operations using TCs, and (ii) applying state-of-the-art numerical error correction (EC) techniques to maintain accuracy. Experimental evaluations on NVIDIA A100, H100, and B200 GPUs show that our CUDA-based implementation consistently outperforms the baseline while preserving algorithmic accuracy.
Data movement bottlenecks have emerged as a dominant performance limiter in modern computing systems. At the same time, scientific detectors are generating unprecedented data volumes: X-ray detectors may soon produce terabytes per second and high-energy physics experiments demand bandwidth on the order of petabytes per second. Streaming compression offers a promising path to reducing data movement overhead, and hardware accelerators can further improve data throughput, while the exploration of system-level hardware compressors remains largely unexplored. This paper presents a preliminary study toward enabling hardware evaluation of streaming compressors. We design and implement a custom hardware accelerator for scientific data compression using modern hardware description languages, providing a complete end-to-end hardware acceleration system for CPU-based platforms. Our prototype features a multi-stage state machine, parallel element processing, and optimized data transfers, achieving 1.45x speedup over a software baseline with comparable quality, with 31% fewer cycles per element and 45% faster compression throughput.
We present an automated framework for online task scheduling on heterogeneous distributed systems, building on a modular parametric scheduler that enables dynamic scheduling decisions based on evolving execution states. Inspired by classical list-scheduling strategies such as HEFT and CPoP, our online scheduler simulates real-time task scheduling using only partial task graph knowledge. We evaluate our online scheduler variants against both their traditional offline baselines and a naive online strategy using a largescale benchmark suite of real-world scientific workflows. Experimental results across different estimation methods and compute-to-communication ratio (CCR) settings show that our adaptive online schedulers consistently outperform the naive approach, achieving performance within approximately 3-5% of an ideal offline scheduler that has full future knowledge (compared to the approximately 10% overhead for the naive baseline).
Foundation models, such as large language models, have become ubiquitous and are employed in many applications. These models are often adapted to a desired domain or downstream task through a fine-tuning stage. Cerebras, the wafer-scale AI accelerator, is a suitable platform for running foundation models. However, existing works utilizing sparse pre-training followed by dense fine-tuning result in dense models, failing to reduce the inference cost, measured in floating-point operations. This paper proposes Phoenix, a solution to enable sparse inference for downstream tasks on Cerebras. Phoenix features an innovative strategy that merges sparseweights with low-rank adapters to enable sparsity without losing accuracy, overcoming the limitations of previous approaches. Phoenix also leverages the Cerebras CS-2 wafer-scale engine to accelerate the inference process using unstructured sparsity methods. We evaluate multiple adaptation scenarios, models, and a range of sparsity levels to demonstrate the effectiveness of Phoenix. Phoenix maintains accuracy comparable to dense baselines even at 50-60% sparsity. Meanwhile, it achieves up to a near 2x reduction in FLOPs and a 1.7x improvement in inference throughput compared to a single NVIDIA A100 GPU during the inference stage.
Understanding the irregular, dynamic communication patterns in HPC applications at scale is critical when evaluating potential software optimizations and hardware architectures. Current systems monitor communication behavior for entire applications as exhaustive traces or general-purpose aggregated statistics. Generally, these approaches often do not scale well and the data gathered is often too generic or inflexible to make specific hardware/software optimizations. This paper describes a new, configurable, histogram-based approach to gathering scalable, high-fidelity monitoring information about HPC communication that we implemented in the Vernier communication monitoring system. This approach enables targeted collection of statistical data about annotated communication patterns for online or offline analysis, benchmarking, or network simulations. We assess these capabilities by collecting communication patterns from several production HPC applications at scale, showing that the resulting statistical representations accurately characterize the communication patterns in these applications, and can be used to provide new insights into communication patterns of complex HPC applications.
We examine the code generator-based MPI correctness benchmark MPI-BugBench (MBB) by analyzing the code coverage it triggers in three tools: MUST, PARCOACH, and clang-tidy. We present our analysis as a complement to MBB’s original design, which is based on pruning the potentially exhaustive test set based on real-world MPI usage patterns. Our assessment identifies two key limitations in MBB’s generated tests: incomplete coverage of MPI features, such as varying-count collectives, and limited structural diversity, such as lack of loops and array-based MPI handles. In addition, the current strategy of MBB’s code generation by increasing test volume alone offers limited benefit for exercising the analysis of these tools in our assessment. To address these gaps, we implemented 34 new tests covering missing MPI features and more varied code structures. The tests exercise previously uncovered analysis code, where a single varying-count collectives test adds 770 covered code lines in MUST.CCS Concepts• Software and its engineering Empirical software validation; Software maintenance tools.→
With the widespread application of Mixture of Experts (MoE) reasoning models in the field of LLM learning, efficiently serving MoE models under limited GPU memory constraints has emerged as a significant challenge. Offloading the non-activated experts to main memory has been identified as an efficient approach to address such a problem, while it brings the challenges of transferring the expert between the GPU memory and main memory. We need to explore an efficient approach to compress the expert and analyze how the compression error affects the inference performance. To bridge this gap, we propose employing error-bounded lossy compression algorithms (such as SZ3 and CuSZp) to compress non-activated experts, thereby reducing data transfer overhead during MoE inference. We conduct extensive experiments across various benchmarks and present a comprehensive analysis of how compression-induced errors in different experts affect overall inference accuracy. The results indicate that experts in the shallow layers exhibit minimal degradation in inference accuracy when subjected to bounded errors. In contrast, errors in the middle-layer experts, which are central to model reasoning, significantly impair inference accuracy. Interestingly, introducing bounded errors in the deep-layer experts, which are mainly responsible for instruction following and output integration, can sometimes lead to improvements in inference accuracy.
We introduce open-source frameworks for deploying and running large language models (LLMs) within high-performance computing (HPC) environments. One such framework, AI-Flux, targets highthroughput batch inference, enabling users to submit LLM requests in an OpenAI-compatible format as traditional HPC jobs. Another framework is based on Ray Serve and it provides dynamic, ondemand allocation of HPC resources for interactive LLM serving via APIs, supporting applications such as chatbots and AI agents. The third framework, Illinois Chat, is a production-grade, alwayson platform for real-time interaction, that relies on a dedicated GPU server for model inference. These frameworks are designed to abstract away underlying computer system complexities, allowing researchers to request and utilize GPU resources for model inference without manual environment setup. We describe these systems and report LLM-specific performance metrics. Results demonstrate that the proposed frameworks enable scalable and resource-efficient LLM serving across both batch and interactive workloads in support of a diverse user needs.
We propose a conditional normalizing flow (CNF) surrogate model to solve generative, many-to-one inverse problems in scientific simulations governed by partial differential equations (PDEs) with time-evolving interactions between heterogeneous materials. We present two case studies: electrostatic potential and heat diffusion, which serve as proxy simulations for generating diverse sets of initial conditions that can reproduce an observed output state (transient or steady). Finally, we provide a comprehensive overview of the synthetic datasets, the model specification, each stage of the experimental workflow, evaluation of training performance, and uncertainty quantification for the generated samples.
The computing continuum has emerged as a promising paradigm for decentralized data processing. This approach brings computation closer to data sources, reducing latency and enabling faster insights. However, managing such distributed systems introduces new challenges, particularly in ensuring the availability and reliability of data across heterogeneous and failure-prone environments. In this paper, we focus on addressing these challenges by introducing DAGonStore as a novel component of the DAGonStar workflow engine, integrating it with the DynoStore wide-area storage system to provide resilient and location-transparent data access. DAGonStore implements reliability and availability schemes based on erasure codes and utilization-aware load-balancing to guarantee that input and output data remain accessible and consistent, even in the presence of storage node failures or disconnections. We validate our approach through different tests, demonstrating that DAGonStore enables scalable and fault-tolerant workflow execution across the computing continuum with minimal user intervention.
As the increasing energy consumption of High-Performance Computing (HPC) systems places greater strain on electric grid infrastructure, operational strategies for load balancing become critically important. Energy-aware scheduling offers a promising solution by enabling HPC systems to function as actively managed loads within the energy grid. Despite extensive theoretical research on this strategy, practical implementations and real-system evaluations remain scarce. To bridge this gap, we introduce a systematic approach to developing, evaluating, and implementing energy-aware scheduling without modifications to Slurm's core scheduler. Our method includes a novel mechanism for per-job power prediction based on Large Language Model embeddings of enriched job scripts, coupled with a lightweight, deployable scheduling strategy. Our predictor reduces per-job power MAE by 15% compared to the current state-of-the-art, and our simulated scheduler shifts 4.0 MWh onto on-site solar without throughput loss. These results demonstrate a clear and practical pathway to production deployment of energy-aware scheduling in HPC.
High Performance Computing (HPC) datacenters must handle realtime streams demanding sub-millisecond latency and bulk transfers requiring sustained multi-gigabit throughput-objectives that inherently compete on a shared network. Achieving both simultaneously requires end-to-end performance guarantees, typically provided by Quality of Service (QoS) that classify traffic, reserve bandwidth, and enforce priorities across every hop. While backbone and Wide Area Network (WAN) providers (e.g., ESnet) already enforce QoS, the local Ethernet ingress "last-mile" in HPC remains best-effort, creating a blind spot where latency accumulates and jeopardizes time-sensitive workflows. We fill this gap with standards-based Differentiated Services Code Point (DSCP) QoS solution on existing leaf-spine switches: packets are marked at the host, queued per class, and shaped on every last-mile hop through to the High Speed Network (HSN) gateway network interface card (NIC). We evaluate our solution in two scenarios representative of HPC traffic: Intra-domain-traffic that stays entirely within the datacenter (e.g., server-to-server flows over the leaf-spine Ethernet network), and Inter-domain-traffic that crosses the datacenter boundary (e.g., instrument Local Area Network (LAN) - WAN - HPC ingress). Our solution yields up to 60% more stable throughput, 30% fewer retransmissions, and tightly bounded jitter-deployable instantly on operational fabrics without hardware upgrades or proprietary extensions, and paving the way for true policy-driven, end-to-end performance in HPC datacenters.
We present early work towards establishing an automated workflow for floating-point error analysis of SYCL kernels. The method leverages the Intercept Layer for OpenCL Applica- tions to record the execution of GPU-targeted SYCL kernels and replay them with CPU runtimes, enabling detailed floating-point error evaluation without modifying the original application. We analyze the force kernel from a large-scale cosmology application code (HACC) using PoCL and Verificarlo, exploring both IEEE-compliant configurations and reduced-precision modes (e.g.,, FP16, TF32, BF16), as well as the effects of the -ffast-math compiler optimization using stochastic arithmetic via MCA and PRISM. By leveraging open tools and standards, this work contributes a reusable path toward broader adoption of floating-point accuracy evaluation in HPC.
This paper describes the development of performance portable batched linear algebra kernels for SN-DG neutron transport sweeps using Kokkos. We establish a new sweep algorithm for GPUs that relies on batched linear algebra kernels. We implement an optimized batched gesv solver for small linear systems that builds upon state-of-the-art algorithms. Our implementation achieves high performance by minimizing global memory traffic and maximizing the amount of computations done at compile-time. We assess the performance of the batched gesv kernel on NVIDIA and AMD GPUs. We show that our custom implementation outperforms state-of-theart linear algebra libraries on these architectures. The performance of the new GPU sweep implementation is assessed on the H100 and MI300A GPUs. We demonstrate that it is able to achieve high performance on both architectures, and is competitive with an optimized multithreaded CPU implementation on a 128-core AMD Genoa CPU node.
The increasing complexity and scale of high-performance computing (HPC) workloads demand innovative approaches to optimize both computation and communication. While OpenMP has been widely adopted for intra-node parallelism and MPI for inter-node communication, emerging SmartNICs introduce new opportunities for offloading communication-intensive tasks. In this work, we extend OpenMP to support MPI kernel offloading to SmartNICs. Our implementation integrates Open MPI communication offloading into the LLVM compiler while utilizing DOCA SDK for efficient interaction with Nvidia BlueField DPUs. Leveraging OpenMP eliminates the need for direct low-level programming, lowering the entry barrier for domain scientists. We demonstrate our framework's versatility by implementing a SmartNIC-enabled version of the MPI OSU micro-benchmarks and improving the execution time of an atmospheric weather simulation by over 18%, thanks to concurrent computation and communication.
Floating-point data is typically compressed at strict error bounds to reduce storage cost while facilitating scientific analyses. Unfortunately, this tends to yield large compressed files. In some cases, however, a user might not need the data at a high fidelity. Progressive compression addresses this issue by refactoring the data into a hierarchical series of increasing fidelity, allowing users to download the data at an initial fidelity and subsequently retrieve higher fidelities. This paper studies a resolution-based progressive compression approach that achieves competitive compression ratios against traditional compression methods. Furthermore, it studies how the progression of resolution affects the quality of the data.
This paper provides an overview of the multi-image parallel features in Fortran 2023 and their implementation in the LLVM Flang compiler and the Caffeine parallel runtime library. The features of interest support a Single-Program, Multiple-Data (SPMD) programming model based on executing multiple "images", each of which is a program instance. The features also support a Partitioned Global Address Space (PGAS) in the form of "coarray" distributed data structures. The paper discusses the lowering of multi-image features to the Parallel Runtime Interface for Fortran (PRIF) and the implementation of PRIF in the Caffeine parallel runtime library. This paper also provides an early view into the design of a new multi-image dialect of the LLVM Multi-Level Intermediate Representation (MLIR). We describe validation and testing of the resulting software stack, and demonstrate that performance compares favorably to another open-source compiler and runtime library: GNU Compiler Collection (GCC) gfortran and OpenCoarrays, respectively.
High Performance Computing (HPC) applications rely heavily on code optimizations to achieve good performance on modern CPU and GPU architectures. Traditional Machine Learning autotuning approaches have demonstrated success in exploring highdimensional spaces, but they often require expensive compile-run evaluations and lack adaptability for large HPC applications. The recent advances in Large Language Models (LLMs) and Agentic AI systems raise intriguing questions about the potential of these approaches to address specific optimization methodologies. This work aims to answer an essential question for the HPC community: "How Agentic AI Systems Compare to Traditional ML Autotuning Techniques?" To address this question, we present a comparative analysis between a traditional ML-based optimization approach and an Agentic AI system, evaluating their respective capabilities and limitations for loop-level optimization. In addition, we introduced a new Agentic AI system named LoopGen-AI using three different Large Language Models: GPT-4.1, Claude 4.0, and Gemini 2.5. A key finding is that LoopGen-AI achieves competitive performance with only a few program runs, the reasoning logs from the agents revealed that their decisions rely heavily on the combination of semantic understanding of the target kernel with dynamic feedback from the environment, highlighting a promising new dimension in performance tuning. In contrast, ML-based autotuners focus on statistical exploration, and require orders of magnitude more runs to reach peak performance. Additionally, our analysis shows that prompt engineering, particularly using Persona + Context Manager patterns, significantly impacts the effectiveness of Agentic AI. Our results indicate that while Agentic AI systems are not yet a complete replacement for ML-based autotuners, it can effectively complement traditional methods.
