The ability of TRAM for detecting parametric faults in a second-order filter selected as a case of study is studied in this work. Particularly, we adopt a low-pass Sallen-Key filter synthesized on a 500nm CMOS technology. We perform the design using diffused resistors, poly-poly capacitors and a full-custom operational amplifier. For fault injection and simulation, we adopt a previously reported fault model. Different combinations of test parameters are evaluated in this paper with the aim of determining the tradeoff between fault coverage and complexity of the test. Our results show that the simultaneous monitoring of peak time and overshoot gives reasonable fault coverage. The monitoring of other test parameters causes (in some cases) an improvement that should be considered as marginal.
This paper presents a VLSI Convolutional Neural Network with special features to implement the Vanishing Point algorithm. The architecture is based on a multi-scale array, with one column processor that implements a neural network with local connectivity, a row processor of SIMD elements that can implement generic convolution and a voting mechanism, which is used by the Vanishing Point algorithm. In addition, a 32-bit 7 pipeline-stage has been designed to sequence all the operations. Simulations of the architecture described in a Hardware description language are shown.
We design and optimize two non-standard dosimeter circuits: an Active Pixel Sensor and a Floating Gate Sensor, for fabrication on a standard CMOS process. An Active Pixel Sensor is found suitable for dose rates down to 3.6 mGy s(-1), with a sensitivity of 7.1 V Gy(-1). A Floating Gate dosimeter is optimized for a sensitivity of 46 mV Gy(-1), with a noise-equivalent dose of 0.2 mGy.
In this work, measurements of the two versions of the 12 nA Low Frequency Oscillator is presented. The circuit designed in a standard 0.6 μm MOS technology with most of the transistors operating in weak inversion, includes self-bias current and voltage references, and can be powered with a wide range supply voltage from 1.2 to 5.0 V. The oscillator is intended as part of the next generation of portable or autonomous devices, powered by microbatteries or energy harvesting systems.
A selectable bandwidth CMOS Low Noise Amplifier (LNA) implemented in UMC 90nm process is presented. The LNA employs two current conveyors as building blocks to implement a wideband UHF (470 MHz to 862 MHz) voltage amplifier. By means of a switch and an LC tank added at the output, the LNA can operate also in the GSM narrowband (1.8 GHz). Using this simple technique it is possible to use only one LNA for both standards. Simulation results validate the proposed circuit. The simulated power gain (S21) is 13 dB for UHF band, and 6 dB for GSM. The input return loss (S11) is better than -10 dB in both modes. The amplifier has a simulated noise figure (NF) of 5.8 dB for UHF band and 6.3 dB when it is working in GSM band. This amplifier draws 3.9 mA from a ±1.2V supply.
The paper presents an optical fiber Bragg grating (FBG) accelerometer, using a modified cantilever beam design to get the highest possible strain in the FBG and a wide natural frequency. This accelerometer modeled a system composed by a mass mounted at the free end of a cantilever beam, which is also attached to an optic fiber whose length is varied by the movement of the mass. The objective is to compare the measured deflection, natural frequency and sensitivity with the predicted ones. The sensitivity and frequency response range has been enhanced compared to the conventional cantilever designs: surface mounted, patch mounted FBG and L-shape. Achieving a sensitivity of about 330 pm/g and a natural frequency of 227.3 Hz.
A quantized bands model capable to generate capacitance-voltage (C-V) curves of MOS capacitors was implemented and numerical details are discussed. This model is applied to the extraction of the dielectric constant of Al2O3 layers with known physical thicknesses by fitting experimental results. A comparison with a continuum band model is presented.
This paper presents a genetic algorithm (GA) based method for designing two second-order active filters, proposed as cases of study. The GA must determine the values of the passive components (resistors and capacitors) of each filter in order to obtain a configuration that minimizes the sensitivity to variations of the same and also presents design errors minor to a defined maximum value, with respect to certain specifications. The optimization problem to be addressed by the GA is a multiobjective optimization problem. In both cases of study, the algorithm runs considering two possible scenarios with respect to the component values. The results show that the GA can get in both situations filter configurations that meet the established criteria.
A new design for an on-chip ionizing radiation sensor is presented. The circuit consists of two source-coupled Field Oxide Transistors biased with the same drain current through a feedback loop, whose offset in the gate voltage is amplified. This paper explains the design criteria for integration of the sensor in a 0.5 μm CMOS process. The design was validated with simulations and showed the expected behavior.
We present the response of a Commercial-Off-The-Shelf (COTS) CMOS image sensor to different ionizing particles, with the aim of developing a low cost radiation detector. We first analyze the images obtained by exposing the imagers to X-rays from 55 Fe, gamma and beta particles from 137 Cs. Then the detector is successfully used to monitor different gamma fluxes produced by the RA6 nuclear research reactor, Argentina, during a startup procedure.
As systems grow in complexity, their verification becomes a bottleneck on the design flow. In this paper we propose a top-down methodology to perform the complete flow from specifications to Register Transfer Level (RTL). Different abstraction levels such as Transaction Level Modeling (TLM) allows early system verification (with simulation or formal methods), reducing the risk of long redesign cycles. The methodology is validated by showing a case study.
The operation of digital circuits from power supply voltages of the order of 200 mV or less imposes that, in general, MOSFETs are biased in the subthreshold regime, characterized by the exponential relation between the control voltages and the current. In this tutorial paper we analyze some of the basic building blocks of digital circuits operating in the subthreshold region. We analyze the basic CMOS inverter as regards the voltage transfer characteristic, dynamic behavior, and power dissipation. To reduce the dependence of the drain current on the process parameters we show some compensation circuits that adjust the body voltage, with a small silicon area penalty. Some properties of the static random access memory (SRAM) are reviewed. Finally, the Schmitt Trigger inverter, which is well suited to replace the standard inverter as a basic building block for ultra-low-voltage operation, is briefly analyzed.
In the nanoscale technologies, the on-chip Power Management design strategy as a part of a System on Chip is becoming extremely important. Because the value of integrated passive components are low the DC-DC converter operates at a switching frequency as high as 200 MHz. The control architecture of a fully integrated Single-Inductor Multiple-Outputs boost like converter in a CMOS 65 nm technology is presented in this paper. The DC-DC converter counts with a step-up and a step-down outputs, but it can be easily extended to more outputs. The circuit implementation of each converter's blocks and the complete system simulation results are presented in this paper.
Particle Filter is an algorithm that provides system state estimation even for non-linear and non-gaussian systems. For applications that require a large number of particles, real time constraint is hard to accomplish since the algorithm is computationally expensive and the resampling step becomes a bottleneck. In this work, a VLSI architecture for particle filtering in real time is presented. The proposed design implements a fraction of the processing using piecewise linear functions and allocates them as global resources. In this way, a large number of processing elements (PE) working in parallel can be instantiated in the design. An example based on a range-only localization using Radio-Frequency identification (RFID) tags is developed to illustrate the approach. The received signal strength indicator (RSSI) is used to estimate the distance between transmitter and receiver. A VHDL RTL model of the processing data flow is implemented and compared to Matlab simulations showing similar results.
Non-Binary Low-Density Parity-Check (NB-LDPC) codes have been shown to outperform equivalent LDPC codes defined over the binary field, especially when they are designed in high order Galois fields GF(q). This however leads to an increased decoding complexity. In this paper, a computationally efficient version of a soft distance algorithm used for decoding (NB-LDPC) error-correcting codes is described. This decoding algorithm uses squared Euclidean distance as the metrics, does not require knowledge of the signal-to-noise ratio of the received signal, and is less complex to implement than the Fast Fourier Transform Sum-Product and the log-sum-product algorithms. It is a simplified algorithm that can be easily implemented on programmable logic technology such as Field Programmable Gate Array (FPGA) devices because of its use of only additions, subtractions and look-up tables, avoiding the use of quotients and products. Simulations results show that the performance is the same as or better than that of the Fast Fourier Transform Sum-Product and the log-sum-product algorithms. Simulations were done over the AWGN, Rayleigh Fading and impulsive noise with a Symmetric Alpha-Stable (SαS) distribution channels.
In this work, the Universal Verification Methodology (UVM) is analyzed through its application in the development of two testbenches for unit verification. The first one targets a First Input-First Output (FIFO) buffer module and employs all the basic UVM components; a scoreboard with a Reference Model and a Functional Coverage collector are also implemented. The second one verifies an I2C EEPROM slave module; a bus functional model for the I2C protocol is defined to facilitate the driver implementation, rising the level of abstraction and allowing the reuse of the verification component for other I2C devices.
Power line communications (PLC) represent a key part of smart grid techonologies. PLC provides a bidirectional, secure, decentralized and cost-effective communication infrastructure to interconnect and control the grid, and also, devices connected to it. Moreover, it is fairly well known that power lines were not designed to transmit information. PLC signals coexist in the medium with different kind of colored and impulsive noises, so, the complexity to achieve high bit rates and low error transmissions are really important. In this paper it is proposed the use of Complementary Sequences to encode transmited data in order to improve the quality and accuracy of the communication. This is done through the implementation of a bidirectional narrowband PLC system designed to transmit encoded information over low voltage networks. Experimental results are conformed by transmissions along more than 100 meters of a university laboratory network, which clearly demonstrates the benefits of the codification process. The main control of the system is carried out by two independent Spartan 6 FPGAs.
This paper provides the general description, design guidelines and implementation issues of a digital Thyristor Gate Control (TGC) system developed for particle accelerator facilities. The present proposal improves the TGC performance by replacing the conventional synchronization method based on a single phase zero crossing Phase Lock Loop (PLL) with a novel three-phase synchronous method known as Variable Sampling Period Filter PLL (VSPF-PLL). The proposal is implemented in a custom board and it is tested in a 6-phase power converter under a very distorted mains.
A method for selecting passive component values for an architecture of distributed power converters that optimize the power extraction from a photovoltaic (PV) device (module, substring, etc.) is proposed in this paper. One of the main factors affecting power extraction efficiency is switching ripple. A technique to determine the switching ripple that propagates from the ladder converter to the PV device is discussed and validated through parametric simulations. A minimum 99% extraction efficiency is obtained selecting the passive components to limit the maximum current or voltage ripples to approximately 10% of the maximum power point (MPP) current or voltage value, respectively.
This paper reports on design and measurement results of a state of the art low-noise and high-gain transimpedance amplifier (TIA) implemented in 0.18 μm TSMC CMOS technology. Thorough design methodology for high gain and low power TIA design for 2.5 Gb/s optical communication circuits family is presented. A noiseless capacitive feedback is proposed and implemented as a noise efficient feedback network for TIA circuits. Besides, analytical noise calculations in this family of TIA circuits are presented and optimum noise criteria are derived. The saturation and instability problem of TIA circuits resulted from DC dark current of the input photodiodes (PDs) is addressed and a circuit level solution is presented. The measurement results of 0.18 μm chip shows bandwidth of 52 kHz to 1.62 GHz, and transimpedance gain of 75.5 dBΩ while dissipating 26.3 mW from a 2.2 V power supply, including the output buffer. Taking advantage of proposed capacitive feedback network and optimum noise criteria, noise measurement results show average input referred current noise of 3.18 pA/√Hz for this TIA in the bandwidth of operation.
