A wideband 8-16 GHz 125 ps trombone true time delay (TTD) cell is proposed, fabricated on 0.18-mu m CMOS technology. The novel implementation of trombone TTD cell provides a positive gain slope to compensate for the increasing insertion loss versus frequency of other TTD cells in a delay chain. The positive gain slope of the proposed TTD cell is achieved by utilizing a center-tapped all-pass network (APN). It has been shown that the input to center point voltage transfer function of the APN can be designed for loss compensation in the TTD block. The proposed TTD cell, in conjunction with a previously introduced 5-bit delay chain, achieves a maximum delay of 250 ps with a flat S-21 magnitude profile. Measurement results of the fabricated TTD cell show less than +/- 5 ps delay error in the intended frequency band. Also, the 5-bit chain achieves less than 4.6 ps delay rms error with better than -0.37 dB/GHz gain slope across the bandwidth of 8-16 GHz. The fabricated chip occupies an active area of 1.46 x 1.75 mm(2) with 27-mA current consumption from a 3.3-V power supply.

An ultrafast step response synchronous buck converter has been developed for battery-powered and hand-held electronic applications. The proposed converter has an impressive settling time of only two clock periods and a 1.8 A output current capability. This fast step response makes the proposed converter an ideal choice for dynamic voltage scaling technique in the mentioned applications. The proposed design utilizes an analog multiplier controller (AMC), which provides an optimum disturbance-damping mechanism to remove any output voltage error in just two clock periods. In addition, the synchronization feature of the AMC buck converter eliminates the electromagnetic interference concern in fast buck converters. In order to realize the proposed controller a multiplier block and a novel residual time generator block are employed. The proposed AMC buck converter achieves a fast 2-2.3 mu s settling time for 1.3 A load step and a 3-3.5 mu s settling time for 1 V reference step with 1 MHz of switching frequency. Furthermore, The AMC buck converter has a high output current density of 1.38 A/mm(2) with 96% peak efficiency. The proposed design has been implemented in a 180 nm bipolar-CMOS-DMOS (BCD) technology with a die size of 910 mu m x 1500 mu m.

This work introduces a highly effective and robust design methodology for the concurrent realization of a high-power, integrated reflective transistor-based limiter and a low-noise amplifier (LNA), incorporating a novel biasing architecture robust against process and temperature variations. To significantly enhance the power handling capability of the limiter while preserving the low-noise performance of the LNA, a transistor-based configuration is proposed, featuring a new leakage reduction technique. Additionally, transistor-level protection mechanisms are implemented in all gain stages to mitigate excessive gate-source voltage swings across all three amplification stages, ensuring minimal degradation of the overall noise figure (NF). The integrated codesigned limiter-LNA employs an innovative bias circuit that tightly regulates gain stage currents, exhibiting only +/- 12% fluctuation under process variations and demonstrating robust thermal performance. A key advantage of the proposed architecture is its inherent out-of-band signal rejection, which eliminates the need for off-chip band-selection filters, thereby simplifying the system design and reducing cost. Fabricated in 0.15-mu m AlGaAs-InGaAs pHEMT technology, the circuit reliably handles continuous wave (CW) input powers exceeding 10 W. It achieves a low average NF of 2.1 dB and delivers 25 dB gain, with an 8 dB gain switching capability while maintaining output-referred linearity merits across the 8.5-10.5 GHz bandwidth. The proposed limiter-LNA demonstrates an average output 1-dB-compression point and third-order intercept points of 14 dBm and 28 dBm, respectively, at 9.5 GHz for both gain modes, drawing 82 mA dc current from 3.5 V supply voltage.

novel and comprehensive circuit model for designing RF and microwave baluns based on the classic Marchand balun structure are presented and analyzed. Various balun circuits with features of small-circuit size and complex-impedance transformation could be devised based on this new model. As a practical demonstration, an X-band image-reject (IR) mixer is designed and implemented in 0.25-mu m GaN technology, whose RF and local oscillator (LO) baluns are realized by novel complex-impedance Marchand baluns. High-LO-RF port isolation of 40 dB observed from the fabricated mixer is an indication of low amplitude and phase imbalances of the LO and RF balun circuits. Furthermore, the low-conversion loss of 6-8 dB measured for the fabricated mixer, reveals proper complex-impedance transformation of the newly developed Marchand balun.

This article introduces a novel resetting oscillator regulator (ROR) control method for low-dropout (LDO) regulators, designed to achieve fast settling times for both load and reference input steps. The proposed ROR integrates a high-speed loop that independently functions as an oscillator in a closed-loop configuration, along with a separate high-rate resetting oscillator. The resetting oscillator reinitializes the internal nodes of the ROR loop, preventing oscillations and enabling the system to function as a high-speed regulator. Compared to prior works, the proposed ROR demonstrates improved load and reference step response speeds while maintaining a simple implementation. Fabricated using a 0.18-mu m CMOS process, the ROR achieves fast settling times of 15 ns for low-to-high and high-to-low reference steps. It also demonstrates settling times of 25 30 ns for a 400-mA load step, utilizing an integrated 50-pF output capacitor. The ROR consumes only 130 mu A of quiescent current and supports a maximum output current capability of 500 mA. The input and output voltage ranges of the proposed ROR are 1.5 1.8 V and 0.9 1.6 V, respectively. In addition, the regulator exhibits a low output ripple of 0.3 mVrms, occupies a compact active area of only 0.08 mm(2) and achieves a low 3.2-fs figure of merit (FOMT).

A wide-input/output-voltage-range buck converter with adaptive light-load efficiency improvement and seamless mode transition for high-voltage applications is presented in this article. The proposed design uses a load prediction structure to eliminate dc current sensor and to ensure high efficiency in the 0.02 similar to 2-A load range. The pulsewidth modulation (PWM) mode has been used for near-full load. Since efficiency degradation at light loads occurs at different levels regarding the input and output voltage, a novel dynamic frequency pulsewidth modulation (DFPWM) with adaptive efficiency improvement mechanism is proposed, which activates efficiency improvement based on the input and output voltage at proper load current. Moreover, pulse frequency modulation (PFM) has been used to guarantee high efficiency in a wider load range. The proposed trimode buck converter has seamless mode change. Input and output voltage ranges are 5 similar to 30 V and 3 similar to 15 V, respectively, which are compatible with automotive and RF applications. Output voltage disturbance is less than 60 mV at 2-A load step with a 15-mu s settling time for 30 to 3 V conversion. Moreover, output voltage disturbance in PWM/DFPWM and DFPWM/PFM mode change is zero and 60 mV, respectively. The proposed design has been implemented on 180-nm BCD technology with a 1.65 mm x 1.80 mm die size.

This paper introduces a reflective, low insertion loss transistor-based limiter based on anew leakage reduction method. The effectiveness of the proposed limiter has been confirmed through simulation and measurement results. Due to its low insertion loss, the proposed limiter is suitable for low-noise receivers. It reflects approximately 70% of the input power, leading to lower temperature rise, when subjected to high incident power, compared to absorptive limiters. Fabricated using a low-noise 0.15-mu m AlGaAs-InGaAs pseudomorphic HEMT (pHEMT) technology, this design allows for co-design with a low noise amplifier (LNA) on the same die. Measurement results have demonstrated that the proposed limiter can withstand up to 5-W continuous-wave (CW) input power without failure in a compact chip area of only 0.8 mm2. Additionally, measurements show a minimum insertion loss of 0.83 dB with 0.17 dB ripple over the frequency range of 4-6 GHz.

This paper presents a new method to enhance the efficiency of a symmetrical doherty power amplifier (DPA) by fully utilizing the current driving capability of a class-C biased peaking amplifier. In this method, with utilization of the passive voltage gain concept, the input matching networks are designed in a way that the peaking path experiences a higher voltage gain than the carrier path, at high powers. As a result, the higher drive voltage of the peaking amplifier compensates for its lower gate bias and identical peak output currents for both amplifiers can be achieved. For demonstration purpose, a two-stage symmetrical DPA with a power utilization factor (PUF) of about unity is designed and fabricated in a standard 0.18-μm CMOS technology. The measurement results at 2.6 GHz show a power gain of 21 dB and an 1 dB compression point of 21.3 dBm. The peak power added efficiency (PAE) is 35% and the PAE at 6 dB power back-off (PBO) is better than 23%.

An ultra-low-noise buck converter for noise-sensitive applications is presented, which utilizes a novel pseudo average current-mode control (ACMC) with an adaptive ramp generator to decrease the baseband noise. Also, in order to suppress electromagnetic interference (EMI) and high-frequency spurs, spread spectrum and secondary filter are used, respectively. The proposed ACMC buck converter suppresses the switching frequency perturbation effect on the output voltage, and as a result in the spread spectrum condition, only a small amount of noise is added to the output voltage in the baseband frequency. For the spread spectrum with an external clock, a phase-locked loop is used, which synchronizes the internal oscillator and adapts the ramp generator slope to suppress spread spectrum baseband noise. The proposed ACMC converter achieves only 58 mu Vrms noise in 100 Hz-100 kHz frequency range. Also, a +/- 10% random spread spectrum architecture suppresses the EMI level by 11 dB while achieving only 88 mu Vrms and 156 mu Vrms noise for internal and external clock synchronization, respectively. The peak efficiency of the converter is 95% and the output voltage disturbance is 100 mV at a 2-A load step with 16 mu s settling time. The proposed design is implemented on a 180-nm BCD technology occupying a 1.65x3.70 mm2 die size.

This article proposes the theory and implementation of an even-harmonic class- $E$ CMOS oscillator that displays an excellent phase noise performance. Starting from zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions, expressions for drain voltage and current waveforms are derived. Based on a 1:1 transformer, a custom-designed tank is proposed, which satisfies ZVS and ZDS conditions for the core transistors, provides high- $Q$ resonances at both fundamental and second harmonics of the oscillation frequency, and yields a passive voltage gain from the drain to the gate of the core transistors. Satisfying ZVS and ZDS conditions reduces the overlap between the voltage and current waveforms of the transistor that increases the power efficiency of the oscillator. Furthermore, it widens the flat span of the semi half-sinusoidal voltage waveform, where the impulse sensitivity function (ISF) is negligible. Therefore, the conversion of the core transistor noise to phase noise is reduced. These features improve the oscillator’s figure of merit (FoM) in comparison with state-of-the-art CMOS oscillators. The prototype of the even-harmonic class- $E$ oscillator is implemented in a 0.18- $\mu \text{m}$ CMOS technology. At 4 GHz, it exhibits a phase noise of −152.75 dBc/Hz at a 10-MHz offset while providing a 10.6% tuning range. The corresponding FoM is 197.9 dBc/Hz. The circuit draws 7 mA from a 0.7-V supply, and the die area is 0.23 mm 2 .

This article presents the theory and implementation of a quadrature and differential RF front-end receiver. Combining balun, low-noise amplifier (LNA), mixer, and oscillator in a single stage, the proposed circuit, named the Blixator, is well suited for low-power applications. The baseband’s transimpedance amplifier (TIA) also shares part of its dc current with the Blixator cell, resulting in sub-milliwatt power consumption. To avoid additional power and area by quadrature LO generation, the I/Q signals are generated at RF, employing the inductors already required for providing the dc current path of the LNA transistors. The expressions for gain, noise figure (NF), and phase noise of the voltage-controlled oscillator (VCO) are derived, and the behavior of the circuit is thoroughly investigated. The prototype of the Blixator receiver is implemented in a 0.18- $\mu \text{m}$ CMOS technology. The experimental results show a NF of 10.5 dB, an IIP3 of −15.5 dBm, at the maximum gain, and an image rejection of 23 dB, which meets the requirements for the Bluetooth Low Energy (BLE) standard. The circuit consumes only 340- $\mu \text{W}$ , from a 0.8-V supply, and its die area is 0.75 mm 2 .

In this paper concurrent design of Schottky diode based limiter and low noise amplifier (LNA), based on noise matching, is investigated to achieve minimum noise figure (NF) of the receiver chain. In design procedure of the LNA, the noise figure is minimum, gain at central frequency is 14.5 dB, and limiter structure tolerates up to 5 W continuous wave input power. In the proposed concurrent design, a pass-band filter is applied at the LNA output to attenuate undesired out-of-band signals. In the proposed design, the limiter-LNA is implemented with a 0.25 µm gate length AlGaAs/InGaAs pHEMT process. Measured noise figure of chain is 2.7 dB and average gain over 8.5–9.5 GHz frequency range and the gain at 9 GHz center frequency are 10 dB and 14.5 dB respectively. The performance results of proposed matching network are compared with traditional 50 Ω matching networks in limiter-LNA with identical circuit specifications.

This article applies a systematic approach based on the normalized determinant function (NDF) theory to analyse stability in multi-loop circuits and to design the required stabilization network. Presenting several provisions, the return ratios are extracted by employing immittance or hybrid matrices (Z, Y, G or H) of active two ports. Using these matrices, instead of the S-parameters, facilitates the selection of an appropriate stabilizer network. As a practical case, a non-uniform distributed amplifier (NDA) is designed and inspected for potential instabilities. The presented procedure detects instability associated with one of the NDA circuit's loops, and an appropriate stabilization circuit is accordingly devised. In order to validate the procedure, the designed NDA is implemented in a 0.1-μm GaAs pHEMT process. As predicted, the measurements show oscillations, once the on-chip stabilization circuit is disabled.

This paper presents a highly-linear transceiver core chip for X-band phased-array systems with two RX and one TX channels. Implemented in a standard 0.18-mu m CMOS technology, the core chip provides 6-bit phase control (with rms error <2 degrees) and 6-bit gain control (with rms error <0.6 dB) both within the 8.5-11.5 GHz frequency band. Improved accuracy is also available by digital calibration in narrowband applications. The receivers achieve a gain of 13.5 dB, an IIP3 of +10.3 dBm, and a noise figure of 8.2 dB, while drawing 170 mA per channel from the 3.3 V supply. The chip also provides an additional low-gain mode which further enhances IIP3 to +19.1 dBm and the input-referred P1 dB to +11.4 dBm. The transmitter gain is about 17 dB with an output-referred P1dB of +12.4 dBm and 160 mA dc bias current. The power consumption of the chip is digitally adjustable to enable the power/performance trade-off necessary for use in different applications. (C) 2019 Elsevier GmbH. All rights reserved.

In this article, a design methodology is presented to realize integrated class-F high-power amplifiers (HPAs). A harmonic-control network (HCN) is proposed to present short- and open-circuit impedances to each transistor employed in the output stage of the HPA at 2f 0 and 3f 0 frequencies. The HCN absorbs the parasitic capacitance of the transistor and lends itself to be absorbed in the matching and power combiner networks, reducing the die area of the HPA. A proof-of-concept 9.7-10.3-GHz class-F HPA was designed and implemented in a 0.25-μm GaAs pHEMT technology with VDD of 6 V. The designed HPA consists of two amplifying stages, and its output stage includes 16 transistors in parallel to provide 39-40-dBm output power. The class-F HPA achieves a 10-W output power and a peak power added efficiency (PAE) of 63% for pulsed-mode operation with a pulse repetition frequency (PRF) of 1 kHz and a duty cycle of 10%. The measured peak output power and PAE in the continuous-wave (CW) operation are 9.3 W and 58%, respectively.

In this paper, the performance of the class-J mode power amplifier (PA) is studied when an auxiliary network performs active load modulation on the main transistor. Load modulation is realized by injecting an additional class-C like current with conduction angle of $\alpha $ to the drain node of the main transistor. The injected current employs a phase shift of $\phi $ with respect to the half-sinusoidal current of the main transistor, and its maximum value is tuned with the size of the transistor used in the auxiliary network. Detailed theoretical formulations are presented for the optimal load impedances of the PA at the fundamental and second-harmonic frequencies. Furthermore, the output power and drain efficiency of the PA are derived, and it is shown that the drain efficiency of the proposed PA can be as high as 96.8% in theory. The optimal values of $\alpha $ and $\phi $ for improving the drain efficiency of the load-modulated class-J PA are obtained, and a design methodology is also proposed to choose the optimal size of the transistor employed in the auxiliary network. To verify the theoretical derivations, a proof-of-concept 0.83 W class-J PA was designed and fabricated in a 0.25 $\mu \text{m}$ GaAs pHEMT process. The designed PA occupies 3.19 mm2 die area, and it achieves 71% drain-efficiency and 50% power-added-efficiency at 10 GHz.

A wideband integrated delay chain chip with 5-bit delay control, maximum delay of 120 ps and 3.9 ps delay resolution, designed and fabricated in 0.18 $$\upmu \hbox {m}$$ CMOS technology is presented. Second-order all pass networks (APN) are used as delay structures in this delay circuit. In the design of the two MSB bits of the fabricated chip, a new design approach is used which allows higher group delay to be achieved with fewer number of passive second-order APN circuits. This would in turn reduce insertion loss of the designed delay control chain. Measurement results of the fabricated delay chain show 12.6–20.5 dB insertion loss and less than 3.3 ps RMS delay error over the intended frequency band from 8 to 18 GHz. The fabricated chip occupies an area of $$1.2\times 2.7$$ mm$$^{2}$$ and has no DC power consumption.

A novel trombone topology has been introduced for achieving controllable true time delay. The prominent aspect of the proposed topology is the ability to provide discrete variable delay with minimum insertion loss variation with delay settings. Furthermore, the effects of source impedance, output load, and line-terminating loads' impedance mismatch on group delay variation are theoretically investigated for the proposed trombone topology. Moreover, based on this new topology, a prototype trombone delay circuit has been designed and fabricated in 0.18- $\mu \text{m}$ CMOS technology, operating over the frequency bandwidth of 8-18 GHz. This 3-bit delay integrated circuit provides a maximum delay of 109.3 ps with 15.6-ps delay step and utilizes conventional passive second-order all-pass network (APN) and novel passive fourth-order APN delay cells. Measurement results indicate an average insertion loss of 18.2-22.5 dB over the intended frequency band with a relatively low loss variation of less than +/- 1 dB for all delay settings. Measured group delay rms error is less than 4 ps. The core of the fabricated circuit occupies an area of $0.9\times2.1$ mm(2) and draws 13.4 mA from a 3.3-V supply.

A wideband integrated delay chain chip with 5-bit main delay control, two error correction bits, maximum delay of 125- and 3.9-ps delay resolution, designed and fabricated in a 0.18-mu m CMOS technology is presented. This delay chain is a cascade of seven passive internal-switched delay blocks which the five main bits are based on novel delay structures. The proposed delay structures are similar to second- ,fourth-, and sixth-order all-pass networks and are robust to mismatch effects of resistive parasitics of transistor switches. Measurement results of the fabricated delay chain show 15.2-23.3-dB insertion loss and less than 3.3-ps rms delay error over the intended frequency band from 8-18 GHz. Input and output reflection coefficients are better than -11 dB for the delay chain including the effect of RF bondwires and pads. The fabricated chip occupies an area of 2.0 x 1.0 mm(2) and has no dc power consumption.