The combination of increasing connectivity to the outside world and the lack of inbuilt security mechanisms has made legacy intra-vehicular networks extremely vulnerable to cyberattacks. Consequently, significant research has been devoted to analysing the impact of potential attacks, yielding datasets crucial for developing effective mitigation schemes like intrusion detection and prevention systems (IDSs/IPSs). Initial research addressing this problem focused heavily on maximising attack detection accuracy (for both known and unknown attack vectors), often relying on large, full-precision machine learning models. However, embedding IDS into complex vehicular electronic systems adds challenges beyond accuracy, including the need for low detection latency (e.g., 2,000 CAN frames/sec), energy efficiency, and minimal overhead in electronic control unit (ECU) resources like silicon area, memory, and processor use. To address these deployment constraints, recent research has focused on lightweight machine learning models that balance high classification accuracy with these practical limitations. In this work, we propose a dual IDS framework comprising both supervised and unsupervised learning-based solutions, each optimised for real-time, resource-constrained deployment on embedded automotive platforms. We present a quantised LSTM-based IDS (QLSTM-IDS) that achieves over 99.9% detection accuracy across various attack types: DoS/Flooding, Fuzzing, and Spoofing/Malfunction, using a single model and two widely-used datasets. The model is trained using the brevitas quantisation aware training library, transformed into a dataflow accelerator with custom blocks compatible with AMD’s FINN toolchain, and synthesised using Vitis HLS. Complementing this, we introduce an 8-bit quantised convolutional autoencoder-based IDS (QCAE-IDS) for detecting previously unseen anomalies that alter CAN-ID sequence patterns, with >99% accuracy. QCAE-IDS is quantised using AMD’s Vitis-AI toolchain. We detail an integration architecture enabling both IDS models to operate on a single FPGA device, bridging the network interface IP and processor system to minimise software overhead. QLSTM-IDS achieves 0.25ms inference latency and 0.8mJ energy consumption, while QCAE-IDS achieves 0.42ms latency and 1.1mJ energy, supporting real-time, efficient detection of both known and unknown attacks on high-speed CAN buses. Both solutions are deployed and evaluated on the ZCU104 SoC (XCZU7EV FPGA), demonstrating a robust, flexible hardware/software co-design for securing modern vehicular networks.
Contrast-Limited Adaptive Histogram Equalization (CLAHE) is widely used in industrial and embedded imaging, yet a fixed Clip Limit often fails to balance detail enhancement and noise suppression across diverse scenes while maintaining stall-free, one-pixel-per-cycle pixel-stream throughput. This paper proposes a deployment-driven, perception-guided software–hardware co-design for CLAHE, where perceptual guidance from offline no-reference image quality assessment (NR-IQA) signals is distilled into a low-dimensional policy that only consumes hardware-observable statistics, and the field-programmable gate array (FPGA) architecture embeds closed-loop control without stalling the main pixel path. On the learning side (offline, in software), Clip Limit tuning is formulated as a Markov decision process (MDP) and learned with Soft Actor-Critic (SAC) using a dual-teacher distillation scheme that transfers privileged NR-IQA guidance to a low-dimensional student policy. Posterior trajectory selection (PTS) and Q4.12 quantization-aware distillation further improve robustness under partial observability and fixed-point inference. On the hardware side, we implement an FPGA single-clock-domain streaming pipeline that integrates feature extraction, student inference, and CLAHE mapping while preserving one-pixel-per-cycle throughput, and we reduce critical-path complexity via division elimination and separable fixed-point interpolation. The controller performs one update per frame and commits the new Clip Limit at the frame boundary; therefore, a five-step horizon corresponds to a five-frame gradual adaptation with intra-frame consistency. Experiments show that the proposed controller is competitive with strong fixed-parameter baselines in mean NR-IQA scores, while reducing failure-sensitive upper-tail degradation using hardware-observable inputs only.
As mobile devices become ubiquitous, the need for improved quality of experience (QoE) continues to place increasing demands on these devices. Delivering consistent and high QoE while managing various applications and user requirements on these energy-constrained devices remains a significant challenge. Dynamic voltage and frequency scaling (DVFS) and display brightness scaling are two commonly used power-saving techniques. We argue that existing approaches are not efficient in maximising user experience, especially in handling a variety of applications with varying requirements while meeting users’ daily battery life expectations. In this paper, we propose an adaptive approach that dynamically adjusts DVFS and display brightness scaling to maximise the user experience by considering the user’s expected battery life and a wide variety of mobile workload characteristics. Our method employs K-means clustering to classify diverse workloads at runtime and then assigns the appropriate DVFS and brightness settings based on the clusters and contexts of the workload and energy budget to achieve the expected battery life. Experimental evaluations conducted on real-world mobile devices demonstrate the effectiveness of our approach, with average improvements in QoE and battery life of up to 9% and 35%, respectively, compared to the state-of-the-art.
Modern clustered (power-island) multicore processors increasingly expose retention as a low-overhead low-power state, yet exploiting it in real-time systems critically depends on whether the scheduler can create sufficiently long cluster-level all-cores-idle windows that exceed a break-even length. This feasibility bottleneck is particularly acute for always-on arbitrary-deadline Directed Acyclic Graph (DAG) workloads, where precedence-induced execution fluctuations fragment idle times and the relative deadline may exceed the period. This paper proposes a retention-oriented scheduling framework for such workloads, consisting of two algorithms with a clear progression. PRES performs design-time planning and constructs a postponable division for each DAG, reshaping execution to aggregate slack into contiguous cluster-level idle windows; a lightweight event-driven runtime then enforces the plan and triggers retention without increasing online scheduling complexity. Building on PRES, PREHS further improves core utilization via multi-DAG merging and intra-cluster spatial sharing, consolidating workload onto fewer active clusters to reduce static/leakage energy while preserving deadline guarantees. We conduct extensive experiments across diverse cluster configurations and DAG structural characteristics, and further include a case study based on an application-derived DAG from a real-world communication/signal-processing pipeline. The results show that, compared with a representative work-conserving baseline with automatic retention/PG, PREHS reduces static energy consumption by up to 65.62%; moreover, under the same resource constraints, PREHS improves task acceptance ratio over PRES by up to 43 percentage points, with the largest gains observed in resource-tight configurations.
