Rowhammer attacks repeatedly activate DRAM rows, causing bit flips in adjacent rows. DDR5 introduced Per-Row Activation Counting (PRAC) to mitigate such attacks; however, its static threshold-based mitigation and unnecessary distant-row refreshes limit efficiency in terms of performance and energy consumption. This paper proposes Dynamic-PRAC, which dynamically adapts mitigation thresholds based on service-queue utilization and refines refresh actions according to row distance. Experimental results show that Dynamic-PRAC outperforms PRAC, MOAT, and QPRAC while reducing the overhead of refresh cycles and energy consumption, achieving up to 63% lower mitigation overhead and 93% lower mitigation energy overhead. Security evaluations further demonstrate that our scheme achieves one of the lowest maximum unmitigated activation counts across different TBO settings.
This paper presents a reconfigurable and energy-efficient digital spectrum shaping signaling (DSSS) for multidrop interfaces, where the output spectrum of the transmitted data is shaped using the 2-times repetitive block transmission to avoid frequency notches in the multidrop channel, thereby achieving a data rate up to 4x the first channel notch frequency. In conventional wireline transceivers (TRX), compensating for frequency notches requires a large number of decision feedback equalizer (DFE) taps at the receiver, resulting in significant area and power overhead. In contrast, the proposed DSSS architecture supports spectrum-efficient reconfigurable dual-mode NRZ/PAM4, reducing required equalization efforts and improving energy efficiency. The proposed scheme and its transmitter (TX) were first validated through event-driven behavioral simulations using XMODEL and verified with equipment-based measurements. Post-layout simulation results in 28nm CMOS process demonstrated 4 Gb/s data rate communicating over a channel having its first > 30 dB notch at 1 GHz, with a 235mV vertical eye opening and a TX energy efficiency of 0.39 pJ/b at 0.8V supply.
Compute-in-Memory (CiM) is emerging as a promising paradigm to design energy-efficient hardware accelerators for AI, addressing the processor-memory data transfer bottleneck. The popularity of CiM can be attributed to their ability to perform massively parallel in-situ matrix vector multiplications (MVMs), the dominant computation in neural networks (NNs). However, NNs used in NLP applications such as Long-Short Term Memory (LSTM) and transformers also frequently perform other operations such as transcendental functions (tanh, sigmoid, and softmax). To that effect, we present MemRaptor, utilizing CiM with magnetoresistive random access memory (MRAM) technology, that can perform both MVM and transcendental functions in the same memory array. MemRaptor overlays a read only memory (ROM) on an MRAM array through hard-wiring the connection of bit-cell with an additional bitline (a bit-cell connected to either of the bitlines but not to both), incurring no array area overhead and a minimal peripheral area overhead. Note, the bitline connection of bit-cell stores the ROM value while the magnetic tunnel junction (MTJ) in the bit-cell stores the RAM data. Particularly, the magnetization state of the 1T-1MTJ bit-cell in the array stores the weight value (RAM data) of the neural network, and the bitline connection of the bit-cell stores the look-up table (ROM data) used for computing transcendental functions. We demonstrate the working of our proposed design through circuit-level simulations for a 64x64 array, using a compact model of CoFeB/MgO PMA MTJ with 120% tunnelling magnetoresistance, 5k Omega R-ON, in 65nm technology. Further, we showcase the advantage of MemRaptor over standard MVM-based CiM accelerator architecture, PUMA, through comprehensive system-level evaluations for LSTM, BERT, and GPT models. Our results show up to 30% and 5.3% improvements in terms of throughput and energy-efficiency, respectively, on an average across different workloads.
Recently, compute-in-memory (CIM) has become a promising architecture for data-intensive applications such as deep learning. However, analog or digital CIM (ACIM or DCIM) faces some design challenges. ACIMs inherently have non-idealities, which lead to significant accuracy degradation. In addition, a substantial amount of power is consumed by analog-to-digital converters (ADC). On the other hand, DCIMs show an exponential increase in power consumption and computing cycles as the operand bit-width increases, particularly due to an accumulation stage. In this paper, to overcome these challenges, we propose a hybrid DCIM-ACIM architecture that consists of a content addressable memory (CAM) as DCIM and a cluster-based multi-cycle ACIM, called CAM-CIM. As a weight mapping strategy, we present a subword split mapping that assigns some MSBs to DCIM for improved accuracy and the remaining LSBs to ACIM for reduced ADC resolution. The accuracy of using the proposed CAM-CIM array is evaluated on various deep learning benchmarks from CNNs to Swin-Tiny. A 65nm CAM-CIM macro with either 3-bit or 4-bit ADCs shows 10.3x and 5.4x improvement in energy efficiency, on average, compared to CAM- and CIM-only architectures, respectively. Compared to recent CIM architectures, CAM-CIM demonstrates 1.4x higher energy efficiency.
Macro placement in the floorplanning stage is crucial as it marks the beginning of the entire VLSI physical design flow. Despite its significant impact on the final design quality, identifying the optimal macro placement for sign-off power-performance-area (PPA) remains challenging and often relies on empirical methods. Although recent algorithms for automatic macro placement leverage the relationships among macros and standard cells, they failed to fully address timing-related objectives. In this paper, we propose a timing-driven macro placement framework that utilizes connectivity and clocked element (e.g., flip-flop) information among macros for clustering and integrates dedicated timing costs throughout the entire process. We first utilize the Louvain algorithm to iteratively conduct multi-level clustering on a directed graph derived from the design RTL, with edge weights assigned based on the ratio of the number of logic gates and clocked elements between macros. At each clustering level, we utilize simulated annealing (SA) to determine the clusters' shape and placement. After the last iteration, we conduct macro placement per cluster using SA with our timing-related cost function. Finally, we refine the macro placement result to escape from the bottom-left arrangement, again guided by the timing-related cost function. Experimental results demonstrate that our macro placement framework successfully improves timing metrics, WNS and TNS, by 16.87% and 18.49% over state-of-the-art open-source macro placement, and by 6.59% and 15.54% over a commercial macro placement engine, respectively.
