Soft real-time applications, including multimedia, gaming, and smart appliances, rely on specific architectural characteristics to deliver output in a time-constrained fashion. Any violation of application deadlines can lower the Quality-of-Service (QoS). The data sets associated with these applications are distributed over cores that communicate via Network-on-Chip (NoC) in multi-core systems. Accordingly, the response time of such applications depends on the worst-case latency of request/reply packets. A malicious implant such as Hardware Trojan (HT) that initiates a delay-of-service attack can tamper with the system performance. We model an HT that mounts a time-delay attack in the system by violating the path selection strategy used by the adaptive NoC router. Our analysis shows that once activated, the proposed HT increases the packet latency by 17% and degrades the system performance (IPC) by 18% over the Baseline. Furthermore, we propose an HT detection framework that uses packet traffic analysis and path monitoring to localise the HT. Experiment results show that the proposed detection framework exhibits 4.8% less power consumption and 6.4% less area than the existing technique.
Silicon photonics-based optical networks-on-chip (ONoCs) have been considered as a competitive alternative to electronic NoCs for chip multiprocessors (CMPs). However, the presence of thermooptic effects may prevent them from maintaining power efficiency advantages over electronic counterparts. To address the thermal issue, some routing schemes based on reinforcement learning have been proposed to reduce the optical power loss. Although thermal-related optical power loss could be minimized by routing packets along paths with the lowest thermal gradients, contention may occur on these paths. In this work, we first propose a contention-aware deadlock-free routing (CDR) for electronic-controlled ONoCs, using Q-learning model for single-objective optimization for contentions. Then we further propose a Q-learning based bi-objective deadlock-free routing scheme (BODR) for ONoCs under thermal variations, to comprehensively improve both the power efficiency and the network performance. Experimental results show that BODR routing can greatly reduce the delay with a small cost of optical power loss compared with the single-objective Q-routing for power optimization. Meanwhile, the proposed method can improve the optical power loss while simultaneously achieving a higher network performance as compared with other traditional adaptive routing schemes.
Big Data, Artificial Intelligence (AI) and other scientific applications use multi-core systems to process data for disease and drug discovery, weather forecast, design automation, etc. However, multi-core systems are not always effective because not all applications are amenable to them, leading to the need for special-purpose architectures, e.g., accelerators. Also, large monolithic multi-core chips are more prone to manufacturing defects that dramatically reduce the wafer yield and increase the cost. The need for specialisation coupled with skyrocketing manufacturing costs led to the introduction of multi-chiplet systems. They integrate a set of heterogenous chiplets within a single package, where each chiplet is a smaller multi-core chip. In addition to on-chip communication within chiplets, now there is a need for an on-package communication infrastructure to facilitate data sharing among chiplets. Copper wire-based Network-on-Chip (NoC) and silicon interposer-based Network-on-Package (NoP) are the preferred infrastructures for on-chip and on-package communications. However, increasing core count within chiplets and diverse communication demands by different chiplets have exposed the limitations of NoC and NoP. Experts reported communication and not computation as the main bottleneck in emerging computing systems. This generated renewed interest in the exploration of NoC and NoP. The first goal of this panel is to discuss recent challenges in NoC and NoP with respect to performance, security and scalability. Then the panellists discuss exciting opportunities presented by the rise of new interconnect technologies, including 3D, optical and wireless; integration technologies, including, silicon interposer and multi-chip module; and computing paradigms, including in-memory, DNA and quantum. The final and most important goal is to engage panellists and attendees in a discussion about recent breakthroughs and innovations, and how the field could be moved forward.
Network-on-Chip (NoC) has become a fundamental building block in modern Chip Multi-Processors (CMPs) and plays a significant role in their performance. Nevertheless, ever-increasing core counts coupled with shrinking CMOS technology increases communication latency in Electrical NoC (ENoC). Radio frequency enabled Wireless NoC (WiNoC) is one of the promising solutions proposed to supplement the ENoC and form a wired-wireless hybrid infrastructure. However, except for Noxim, there is no other open-source simulation infrastructure for WiNoC exploration. This work implements a cycle-accurate WiNoC infrastructure in a popular ENoC simulator. The infrastructure is modular and scalable for any network size. Among other important features, it implements a broadcast-enabled one-hop communication and a credit exchange mechanism for radio hubs to avoid packet re-transmission. It is a work in progress and hence supports easy integration of new features for exploration.
In response to growing application diversity, System-on-Chip (SoC) architectures have become increasingly heterogeneous, with diverse cores and accelerators, as well as non-uniform memory systems. However, existing open-source design frameworks for SoCs and NoCs (Network-on-Chips) have been unable to facilitate design exploration of heterogeneous SoC architectures with irregular NoCs. We present Constellation, a new NoC RTL generator framework designed from the ground up to support integration in a heterogeneous SoC and evaluation of highly irregular NoC architectures. Constellation implements a highly decoupled specification system that allows an architect to specify an exponentially large design space of irregular virtual-channel wormhole-routed NoC architectures. Additionally, Constellation provides a diverse set of systems, regression tests, and evaluation tools to provide confidence in the correctness and performance of the generated hardware. Constellation is open-sourced and integrated into the Chipyard SoC design framework, allowing full-system exploration of heterogeneous SoC architectures with irregular memory fabrics.
