To provide good classification accuracy and meet challenging design constraints, image classifiers deployed in embedded systems are typically implemented using convolutional neural networks (CNNs) accelerated with specialized inference accelerators. We propose a supernet-based neural architecture search (NAS) method to automate the design process of CNNs executed on the Hailo-8L accelerator, an expanding module for the Raspberry Pi Kit. The method utilizes a multi-objective genetic algorithm in conjunction with a pre-trained supernet and latency predictor to accelerate the evaluation of candidate CNNs. The latency predictor is trained using a collection of generated CNNs whose exact latency is determined directly on the Hailo-8L accelerator. The method is evaluated using CIFAR-100 and ImageNet-100 benchmarks and provides classifiers with competitive accuracy-latency trade-offs.
Field-programmable gate arrays (FPGAs) are widely adopted as accelerators for compute-intensive applications. In modern FPGA flows, floorplanning provides coarse-grained region constraints, but commercial tools offer no automatic support, requiring designers to manually define partition regions that substantially impact placement and routing. This paper presents a fully automatic framework that generates resource-guided floorplanning constraints to improve the clock frequency of FPGA designs. The framework employs a divide-and-conquer strategy with nonlinear optimization for resource-aware region assignment, exploiting FPGA heterogeneity in a device-agnostic manner and producing constraints that integrate into commercial toolflows. The framework has been integrated into Vivado and tested with nine benchmarks and two platforms, improving the maximum clock frequency by 11.4
As computing needs are expanding, scaling up the general-purpose computing resources is limited by energy consumption and efficiency. Coarse-Grained Reconfigurable Arrays (CGRAs) are a solution to that challenge: they are versatile digital architectures, capable of achieving near-ASIC level of energy efficiency without sacrificing reconfigurability. However, CGRAs are limited to the instructions they were built with. Unsupported operations must be emulated, which severely impacts performance. To preserve CGRAs inherent features while enabling higher reprogrammability, we propose MultiGRA: an architecture template that expands the fixed CGRA’s instruction set by including embedded FPGA fabrics (eFPGA) inside the CGRA as finely reconfigurable zones. The eFPGA areas are capable of implementing application-specific operators, specialized at compilation time. This approach avoids overprovisioning computing resources, since the architecture can be freely retargeted. We investigate two of the many integration possibilities of eFPGAs in CGRAs with the respective gains. Examples of post-synthesis ASIC area measurements are provided to show integration feasibility. In a case study comparing CGRAs and MultiGRAs, MultiGRAs show up to 40
Pre-trained language models (LMs) deliver strong performance across a wide range of Natural Language Processing (NLP) tasks but remain costly to deploy on embedded devices due to their high memory and compute requirements. A widely used strategy for adapting LMs to resource-constrained devices is aggressive quantization. At low bit-widths, mixed-precision schemes, where different components of the model use different numerical precisions, offer an effective balance between compression and accuracy. In this work, we evaluate the impact of mixed-precision quantization for inference on the BERT language model. Unlike prior studies that often overlook activation quantization, our evaluation systematically explores mixed-precision configurations for both weights and activations. We also examine the effects of quantizing the embedding layer, which is commonly limited to token-weight quantization. Evaluated on the SQuAD and GLUE benchmarks, our approach achieves substantial reductions in memory and computational cost without sacrificing accuracy.
The growing demand for secure healthcare services in medical IoT networks has raised the need for robust anomaly detection systems, with autoencoder (AE) as a compelling solution. Although mapping of neural networks on FPGAs is well-known, selecting a suitable High-Level Synthesis (HLS) framework for a particular use case remains a challenge. This work explores the trade-offs between two well-known, open-source HLS frameworks: hls4ml and FINN by evaluating non-functional metrics for deploying AEs. Our results highlight that hls4ml achieves roughly 10× lower latency and 3× higher throughput as compared to FINN. On the other hand, FINN provides a comprehensive, automated end-to-end solution for deploying quantized networks on FPGA with up to 80
