The growth of cloud computing has introduced new challenges in data security and privacy. As data-leakage attacks exploiting hardware vulnerabilities grow, the demand for confidential computing and secure architectures has intensified. Trusted Execution Environments (TEEs) address these concerns by providing hardware-enforced isolation to protect data in use. This research aims to develop scalable techniques for verifying firmware-hardware interactions for at-scale TEE implementations using Intel® Trusted Domain Extensions (TDX) technology as a case study. TDX introduces a SEAMCALL instruction for the Virtual-Machine Manager (VMM) to invoke the TDX Module firmware, the security services module of TDX that helps enforce security policies. The challenges in formally verifying the TDX Module firmware are: 1) developing a formal specification for its correctness, 2) modeling the TDX-capable hardware that it interacts with, and 3) developing scalable firmware verification techniques. We show how key firmware operations in the TDX Module are realized through flows, i.e., a series of calls to the SEAMCALL instruction, each of which invokes a specific function. We provide a specification for each TDX Module function invoked by the SEAMCALL instruction, and independently verify them using an abstract model of the hardware. Further, we provide a specification for each flow and use these individual function-level proofs in a modular verification methodology to verify complete flows. We have implemented our modular verification technique using an open-source software model checker (CBMC), identified a set of important flows, and demonstrated the successful verification of these flows within a reasonable time. We also contrast it with direct (non-modular) verification, which often fails to complete.
NOR flash memory is widely used as a non-volatile storage in Internet-of-Things (IoT) devices, often holding proprietary firmware and sensitive user data. However, even after applying logical sanitization before device disposal, residual data can persist in the storage medium, posing a significant risk of post-sanitization data leakage. In this work, we present a detailed investigation of data remanence and data retrieval techniques in sanitized NOR flash chips. We find that charge-trap NOR flash exhibits data imprinting, leading to substantial leakage: on commercial MirrorBit devices, more than 80 % of previously stored content can be reconstructed from sanitized sectors using partial-erase operations. The extent of leakage depends strongly on device aging and wear level. Floating-gate NOR devices, in contrast, showed no imprinting under identical procedures. These results indicate that current sanitization practices may be insufficient for charge-trap NOR, posing confidentiality risks for firmware and user data at device end-of-life. We investigate the underlying device-physics mechanisms and propose practical mitigation strategies, including periodic data refresh and thermalassisted sanitization.
Embedded systems are increasingly targeted by sophisticated malware, but resource constraints and heterogeneous hardware make conventional defenses ineffective against stealthy attacks. We present RuntimeShield, a runtime anomaly detection framework that leverages the on-chip power distribution network as a hardware trust anchor for embedded system security. Lightweight time-to-digital converter sensors embedded in the power distribution network capture high-resolution power traces. These measurements are analyzed by EchoDropNet, an autocorrelation-enhanced, multi-scale CNN designed to extract stable features from weak and noisy side-channel signatures. We implement RuntimeShield on RISC-V, ARM (A9/A53/R5), and MicroBlaze and evaluate it on 25 BEEBS benchmarks plus open-source workloads. various attacks, RuntimeShield achieves 96.85% runtime detection accuracy with low overhead, demonstrating a practical path to on-device protection for embedded systems.
Dynamic Thermal Management (DTM) stabilizes thermal and power behavior of Multi-processor System-on-Chips (MPSoCs) through run-time monitoring. However, its reliance on comparisons against static thresholds leaves the control loop vulnerable to both malicious interference and aging-induced drifts. In order to demonstrate such vulnerability, in this paper, we propose a novel analog thermal Trojan that targets the temperature-to-current conversion (TCC) unit without leaving any digital footprint. The proposed analog Trojan specifically introduces biases into the TCC unit at the core of MPSoCs' thermal sensing to alter DTM's thermal decisions. To counter the attack, we introduce HeatGuard, a system-level thermal monitoring framework that couples synchronized thermal information with lightweight machine learning for run-time anomaly detection. HeatGuard enforces two adaptive security protocols: credit-based anomaly control that maps trust to DTM actions, and logical trust zoning that localizes mitigation via zonespecific threshold adjustments. Evaluations based on standard benchmarks e.g., PARSEC/SPLASH-2 running on prototypical MPSoCs reveal that HeatGuard successfully maintains the chip's thermal safety while preserving its performance, in particular: i) HeatGuard caps temperature peaks from 83° C to 77° C, ii) it shortens average recovery time from 200 to 89 cycles, iii) it reduces the number of overheating events from 20 to less than 3, and the temperature variance by 61%, iv) it sustains 96.3% of the baseline throughput, and v) lastly, it achieves 94% attack detection with ${7 3 \%}$ fewer false DTM activations.
RowHammer is a well-known disturbance-induced DRAM attack where repeated row activations cause bit flips in adjacent rows. With increased read activity in emerging highbandwidth flash (HBF) architecture combined with aggressive vertical scaling, similar disturbance-induced vulnerabilities are becoming a growing security concern in 3D NAND technology. This paper presents the first systematic evaluation of RowHammer susceptibility in commercial 3D NAND flash using a novel read-disturb attack that amplifies hot carrier injection by deliberately shifting read-reference voltages. Experiments on a 96layer 3D NAND device with Quad-Level-Cell (QLC) storage configuration reveal that the raw bit-error rate (RBER) in a victim page can exceed ECC limits after only 20 k read stress for fresh block and in 7 k read stress for 1 k program-erase cycled block. Furthermore, we show that a single aggressor page can corrupt multiple victim pages across adjacent physical layers due to the sub-block organization of modern 3D NAND. These findings demonstrate that disturbance-induced cross-layer corruption is an emerging security risk in advanced NAND flash technologies.
