Content Addressable Memories (CAMs) enable fast pattern matching and are widely used in modern systems. ReRAM-based CAMs (ReCAMs) offer high density, low power, and non-volatility; however, the interaction between intrinsic ReRAM defects and CMOS process variations introduces complex faulty behaviors that challenge conventional diagnosis. Moreover, ReCAM arrays are highly susceptible to process, voltage, and temperature (PVT) variations, whose impact is amplified in computation-in-memory (CiM) architectures due to analog sensing. Accurately localizing faulty cells in ReCAMs is particularly challenging because all cells in a row share the same match-line (ML), while only small ML voltage differences reveal location-dependent fault behavior. This paper presents a variation-aware Design-for-Testability (DfT) framework for precise ReCAM fault localization. The proposed DfT circuitry combines a tunable OpAmp and ADC with an iterative diagnosis flow that adaptively adjusts gain and sampling time in a multi-step process to improve diagnostic resolution under PVT variation. Results show that favorable voltage and temperature operating points can be exploited to accelerate diagnosis and reduce sensing overhead, while a partitioning-based diagnosis strategy reduces required gain by approximately 80% for large arrays. Across diverse fault scenarios and PVT corners, the proposed method localizes faults in only 2–8 diagnosis iterations and achieves approximately 2.29× lower diagnostic latency than March-based approaches, while incurring only 0.36% area overhead and up to 6.3% test-power overhead.
The floating body effect (FBE) degrades the retention characteristics of three-dimensional (3D) dynamic random-access memory (DRAM) by increasing the body potential of the access transistor. In this work, retention degradation in 3D DRAM with a gate-all-around (GAA) access transistor is systematically investigated using mixed-mode TCAD simulations. Both dynamic and static retention characteristics for the ‘1’ and ‘0’ states are analyzed as functions of channel thickness (TCH) and channel width (WCH) to assess scaling effects, while explicitly accounting for the quantum confinement effect (QCE). Based on this analysis, the optimal TCH and WCH that balance FBE suppression and on-state current degradation are identified. A duty-cycle-controlled pulse scheme (DCPS) is proposed to quantitatively decouple the FBE-induced retention degradation from quasi-static leakage contributions. In addition, a comparative study of silicon and amorphous oxide semiconductor channels is conducted to elucidate material-dependent FBE and retention mechanisms.
As DRAM technology continues to scale, process-induced chlorine (Cl) contamination has become an important reliability concern because residual Cl near the Si/oxide interface can promote interface defect generation, near-interface trap formation, and cell-level electrical instability. In this work, residual oxide engineering is investigated as a process-compatible strategy to suppress Cl diffusion toward the active silicon region in advanced DRAM structures. Building on prior oxide-based Cl mitigation approaches, this work provides quantitative material and electrical evidence that controlled WOx formation on landing-pad tungsten and intentional residual oxide retention in selected air spacer regions reduce Cl incorporation within the existing DRAM fabrication flow. Chemical and electrical analyses show that increased WOx formation reduces the Cl concentration in the active silicon region by approximately 20%, while controlled residual oxide retention in the air spacer region further decreases Cl incorporation by approximately 51%. The reduction in Cl penetration is accompanied by a corresponding decrease in 1-row distable fail bits, indicating a strong correlation between interfacial Cl incorporation and DRAM electrical reliability. These results suggest that residual oxide engineering can mitigate Cl-associated reliability degradation without increasing process complexity, providing a practical route for improving single-bit failure characteristics in advanced DRAM fabrication.
Electromigration (EM) is an important wearout mechanism for semiconductor circuits. Designers must ensure that interconnect networks do not fail before the required lifetime for the circuit. The design rules given to designers related to electromigration (EM) of interconnects are derived from Black’s model for EM. They are calculated based on empirical experimental data during technology development. Designers have more margin and flexibility if the design rules are based on the more modern physics-based Korhonen model, which accounts for interactions among interconnect segments. This paper demonstrates that the Korhonen model can be calibrated with the same number of wire geometries, current densities and temperatures as Black’s model and explains the calibration procedure needed to extract all relevant parameters. The number of parameters that must be determined for the Korhonen model is reduced from 14 to 4 using the proposed method. The reduced model captures all physical behavior incorporated in the partial differential equations of the Korhonen model. The reduction in the number of parameters simplifies calibration during technology development.
This study systematically investigates the single-pulse surge current capability of 1200 V SiC MOSFETs under various gate bias conditions, and further explores the degradation mechanism induced by repetitive surges. Experimental results demonstrate that the surge current capability varies with the gate voltage, which is attributed to the current through the channel during surge conditions. Meanwhile, under repetitive surges, threshold voltage (VTH) drift and bipolar degradation exert competing effects on the on-state resistance (RDS(ON)) across different gate bias conditions. Subsequent experiments confirm that the variations in VTH are attributed to the degradation of the SiC/SiO2 interface, as further supported by capacitance-gate (CG-VG) characterization after surge stress. Notably, the source-drain voltage drop (VSD) shows a continuous increase due to bipolar degradation caused by repetitive surges, as confirmed by reverse recovery analysis. Overall, this paper provides deeper insights into the performance degradation behavior of SiC MOSFETs under repetitive surges.
