Year 2013 demonstrated a considerable manufacturing challenges to enable the roll out of RF 4G systems. The popularity of utilizing the High chip capacitor for increased VBW tested the resources for both RF assembly in Freescale and the chip manufacturer and subcontractors associated with chip capacitor production. It was demonstrated that the existing chip capacitor device, while designed well, required several enhancements to increase final product assembly quality while reducing the significant CLC footprint. The initial chip capacitor design utilized a standardized ceramic build process needed plating format which in the long run contributed to chip shorting at final assembly due to the existing chip capacitor prone to get solder short and supplier not able to provide consistent solder pattern. To remedy this design, the chip cap processing was radically redefined to produce a chip cap with reverse electrodes and an in-house solder foil process. To date, the new capacitor has been introduced in over a dozen RF products and is being utilized in significant run rates to produce the higher margins needed in this competitive environment.
Void of solder joint can be considered to be one of the main defects in electronic assembly. The existence of void will influence not only the reliability of solder joint, but also the electrical, mechanical and thermal properties of solder joint. X-ray is the traditional method to analyze solder void. The inspection criteria to void are subjective, different customers have different requirements to the void performance of the product. Although the theory of forming void is known, different cases need different actions to get optimized void performance. The main objective of this paper is to study how much the application process can impact the void performance independently. The process parameters investigated in this study mainly include printing parameter effect, reflow profile effect and heating mechanism effect on void formation of solder joint.
Current-induced failures in fine pitch Sn micro bump with Cu pillar have been investigated under a current density of 3.2×104 A/cm2 and temperature of 150°C. This process takes place in 2000 hours of electromigration test. Intermetallic compound formation, kirkendall effect, and crack contributed to this failure. There are two stages of failure mechanism for Cu pillar with micro-bump during current stressing. In first stage, the whole Sn solder was transformed into intermetallic compound and kirkendall voids were formed at the interface between the Cu pillar and Cu3Sn intermetallic compound. In second stage, the Kirkendall voids coalesced into larger porosities then formed continue crack by current stressing, led to leading bump resistance increased.
Corrosion reliability of electronic products is a key factor for electronics industry, and today there is a large demand for performance reliability in large spans of temperature and humidity during day and night shifts. Corrosion failures are still seen due to the effects of temperature, humidity and corrosion accelerating species in the atmosphere, and moreover the surface region of printed circuit board assemblies is often contaminated by various contaminating species. In order to evaluate the level of humidity at which failures such as electrochemical migration start to appear on printed circuit board assemblies, a study of combined electric field, hygroscopic contamination and humidity on inter-digitated test comb patterns contaminated with sodium chloride and further exposed to increasing humidity has been performed. Results showed a significant increase in leakage current when only 70-75 % RH was reached, corresponding to the deliquescence relative humidity level of NaCl. The overall effect of climate (humidity and temperature) has been studied on the internal climate of typical electronic enclosures. The varied parameters included material used for casing, s ize of opening, differential humidity, and temperature effects simulating day/night, and the use of desiccants.
Printed interconnects on flexible substrates using copper nanoparticles ink is attractive because of its lower material cost, lower electrical resistivity and higher electromigration resistance as compared to gold or silver-based ink. However, Cu nanoparticles oxidize easily during the sintering process, which has an adverse effect on its quality and reliability. Thus, it requires process modifications such as sintering in an inert environment to reduce the oxidation effects. In this paper, the properties of nano-sized Cu particles ink-jet printed conductive films that were sintered in N 2 environment are investigated. The sheet resistance and microstructure of the Cu films were monitored as a function of temperature.
