Year 2013 demonstrated a considerable manufacturing challenges to enable the roll out of RF 4G systems. The popularity of utilizing the High chip capacitor for increased VBW tested the resources for both RF assembly in Freescale and the chip manufacturer and subcontractors associated with chip capacitor production. It was demonstrated that the existing chip capacitor device, while designed well, required several enhancements to increase final product assembly quality while reducing the significant CLC footprint. The initial chip capacitor design utilized a standardized ceramic build process needed plating format which in the long run contributed to chip shorting at final assembly due to the existing chip capacitor prone to get solder short and supplier not able to provide consistent solder pattern. To remedy this design, the chip cap processing was radically redefined to produce a chip cap with reverse electrodes and an in-house solder foil process. To date, the new capacitor has been introduced in over a dozen RF products and is being utilized in significant run rates to produce the higher margins needed in this competitive environment.
Void of solder joint can be considered to be one of the main defects in electronic assembly. The existence of void will influence not only the reliability of solder joint, but also the electrical, mechanical and thermal properties of solder joint. X-ray is the traditional method to analyze solder void. The inspection criteria to void are subjective, different customers have different requirements to the void performance of the product. Although the theory of forming void is known, different cases need different actions to get optimized void performance. The main objective of this paper is to study how much the application process can impact the void performance independently. The process parameters investigated in this study mainly include printing parameter effect, reflow profile effect and heating mechanism effect on void formation of solder joint.
Current-induced failures in fine pitch Sn micro bump with Cu pillar have been investigated under a current density of 3.2×104 A/cm2 and temperature of 150°C. This process takes place in 2000 hours of electromigration test. Intermetallic compound formation, kirkendall effect, and crack contributed to this failure. There are two stages of failure mechanism for Cu pillar with micro-bump during current stressing. In first stage, the whole Sn solder was transformed into intermetallic compound and kirkendall voids were formed at the interface between the Cu pillar and Cu3Sn intermetallic compound. In second stage, the Kirkendall voids coalesced into larger porosities then formed continue crack by current stressing, led to leading bump resistance increased.
Corrosion reliability of electronic products is a key factor for electronics industry, and today there is a large demand for performance reliability in large spans of temperature and humidity during day and night shifts. Corrosion failures are still seen due to the effects of temperature, humidity and corrosion accelerating species in the atmosphere, and moreover the surface region of printed circuit board assemblies is often contaminated by various contaminating species. In order to evaluate the level of humidity at which failures such as electrochemical migration start to appear on printed circuit board assemblies, a study of combined electric field, hygroscopic contamination and humidity on inter-digitated test comb patterns contaminated with sodium chloride and further exposed to increasing humidity has been performed. Results showed a significant increase in leakage current when only 70-75 % RH was reached, corresponding to the deliquescence relative humidity level of NaCl. The overall effect of climate (humidity and temperature) has been studied on the internal climate of typical electronic enclosures. The varied parameters included material used for casing, s ize of opening, differential humidity, and temperature effects simulating day/night, and the use of desiccants.
Printed interconnects on flexible substrates using copper nanoparticles ink is attractive because of its lower material cost, lower electrical resistivity and higher electromigration resistance as compared to gold or silver-based ink. However, Cu nanoparticles oxidize easily during the sintering process, which has an adverse effect on its quality and reliability. Thus, it requires process modifications such as sintering in an inert environment to reduce the oxidation effects. In this paper, the properties of nano-sized Cu particles ink-jet printed conductive films that were sintered in N 2 environment are investigated. The sheet resistance and microstructure of the Cu films were monitored as a function of temperature.
In order to assess the feasibility of a more mass-manufacturable process, IMEC has developed microbump technologies down to 10μm pitch. The micro bumps are based on Cu/Ni/Sn semi additive plating and built at wafer level using a process fully compatible with standard packaging infrastructures. Different test materials with 15, 10 and even 5μm pitch Sn microbumps were processed for a total amount of 640 × 512 (VGA), 1024 × 768 (XGA) and 3072 × 3072 pixels respectively. The microbumped Si chips were assembled with glass chips, InGaAs and HgCdTe compounds and subjected to thermocycling reliability evaluation.
This paper presents study on electrical characteristics of active die embedded substrate that is embedded active devices inside substrate. Active die embedding substrate samples are fabricated using embedding process that consists of lamination process, laser drilling at the electrode Cu pads of active device, electroless Cu plating formation process such as photolithography, electrolytic Cu plating, and etching. Interconnection reliability between external pad of substrate and pad of embedding active devices is evaluated by cross-section and in-circuit test of active die embedding substrate using temperature cycle (T/C) test (-55/+125°C, 1000cycle).
In this work, a test vehicle of 3D stacking structure using through glass vias (TGVs) interposer as major interconnect has been designed and fabricated. Through the optimum TGV filling process for tapered via, chemical mechanical polishing (CMP) process on heterogeneous materials (glass and copper) and 3D structure assembly process, the test vehicle is successfully built and the measured electrical resistance of TGV shows fair agreement to theoretical value. After that, thermal cycling test is employed to evaluate the reliability of TGVs in the 3D structure. Results show that robust 3D stacking structure with glass interposer has been developed successfully in this study.
Cu bond wires in microelectronics have great potential but also provides several challenges. The acceleration factors or failure mechanisms in reliability tests are somewhat different with respect to gold wire bonding which, using unchanged but not validated test conditions and duration requirements, may lead to non-justified failures.With copper wire technology, the intermetallic compounds (IMC's) that form between the bond ball and the bond pad change in composition and corrosion behavior when compared to the gold wirebonding IMC's. When exposed to high temperatures, high moisture levels and high bias, these three different stress factors can add up to very high acceleration factors. When a product or material system fails in this test the question arises what the acceleration factor actually is and how this test compares to application conditions where temperatures may also rise significantly while high humidity levels may still be present and bias is applied. This could the operational startup phase after a long time of being in off or standby stage. The product will suddenly heat up due to the internal heat generation but moisture might still be present in the package. Combined with a high bias voltage this could lead to conditions as seen in the HAST test. To make a comparison between application and test, data was collected on the moisture properties of several molding compounds as a function of temperature. This data was then used in combination with thermal transient simulations of a product in application to compare actual moisture levels under use conditions to moisture levels in test.The simulation shows that the HAST test condition never occurs in the actual application and that the test condition is unrealistically accelerating due to the very high moisture loading. Less extreme conditions will be proposed and discussed. Finally some actual corrosion data will be shown that proof the validity of the simulation results.
Real-time ultrasound guidance during neurosurgery is a novel and sought-after technique that enables imaging data to be acquired with improved precision during surgical intervention. Surgical needles that are inserted in the tissue of interest can be guided using the real-time graphical information collected by an embedded ultrasound transducer. The miniaturisation capabilities of modern manufacturing technologies allow the fabrication of ultrasound probes that are small enough to be fitted in needles conventionally used in surgical practices (down to ~2 mm inner diameter). High lateral resolution may in fact be achieved by producing miniaturised ultrasound transducer arrays with a series of emitting/receiving elements, each electrically isolated from the others. To guarantee the functionality of such devices, a series of independent electrical interconnections must be implemented that enables the external driving electronics of the imaging system to be connected to the miniaturised ultrasound probe array. This paper presents a novel interconnection scheme designed to interface ultrasound probes integrated in surgical needles with the driving electronics. The presented solution utilises a flexible printed circuit board carrying the electrical tracks and a bonding technique with an anisotropic conductive paste.
Band-pass filters with low insertion loss and high frequency selectivity are widely used in the modern electric device and communication systems. With the requirement of the electrical system miniaturization, embedded filter was proposed because of its light weight and excellent performance. In this paper, a fully embedded VHF band-pass filter with bandwidth from 280 MHz to 400 MHz is designed and fabricated based on the BaTiO3-epoxy composite film. The filter is composed of a power plane with cross coupled microstrips and a double helical ground structure (DGS). The size of the band-pass filter is 5mm× 5 mm. It was embedded in a multi-layered FR-4 packaging substrate through the PCB manufacturing process. The measured results of insertion loss and return loss are similar to the simulated results. The measured results shows that the insertion loss is no more than 3.8 dB in pass-band and over 10 dB suppression is obtained at above 1.2 GHz, which is important for the practical application in communication. The embedded band-pass filter using BaTiO3-polymer film as a substrate is a new way for electronic system miniaturization.
Thermoset-based adhesives are used as thermal and electrical interfaces. These adhesives are filled with different particles in order to meet the requirements of heat transfer and electrical properties. In automotive applications, they are required to have excellent adhesion since bulk cracking and/or delamination may precipitate other electrical, thermal or mechanical failure mechanisms. With the help of finite element analysis, it is possible to calculate the behavior of the joint and to locate regions of stress and strain concentration where failure is expected to initiate. However, the accuracy of numerical calculations is dependent on the validity of the material models used in the analysis to describe the deformation behavior of the adhesive and adherents. Linear elastic (LE), elastic-plastic (EP) and linear viscoelastic (LVE) material models are frequently used in microelectronics industry. However, up to now in microelectronics industry, there is no work where the limitations of these material models are discussed. The present paper addresses the above issue. We will show the limitations of LVE models and propose a nonlinear viscoelastic (NLVE) model which is capable to describe the large strain behavior of the observed material behavior. Although the NLVE model is illustrated for an adhesive, similar behavior is also observed at other organic materials such as molding compounds and lamination foils. Thus, the suggested NLVE material model has the potential to be applied to a very wide-range of materials. The authors present LVE (between -40°C and 200°C) and NLVE (at 25°C and 100°C) characterization and modelling of the adhesive. For LVE characterization, dynamic mechanical analysis (DMA) and pressure-volume-temperature (PVT) experiments are used. Results are combined to obtain a LVE model which is described by the Prony terms and shift function. Validation of the LVE model is performed at small and large strains with the help of a newly designed dogbone geometry, which is developed in the course of this work to eliminate the disadvantages of the existing DIN EN ISO 527-2 standard. For validation, static tensile tests (STT) and static tensile tests with stress relaxation segments (STSR) up to failure are used. It is found out that the LVE model is capable of predicting the mechanical behavior of the adhesive only at small strains and fails to represent the highly nonlinear mechanical behavior. As it is crucial to predict the adhesive strength at large strains, already obtained STT and STSR results are used to fit the Bergstrom-Boyce (BB) NLVE material model. It is shown that the BB model can accurately describe the material behavior which is observed from STT and STSR experiments. In order to validate the BB model, static tensile tests with creep segments (STCR), which are not previously used for the calibration of the model, are used. A comparison of LVE and NLVE material models is also presented for the STCR simulations. In order to check the behavior of the BB model at temperatures other than the material model input temperatures (25°C and 100°C), STCR experiments at 70°C are also performed and simulated. In all cases, when compared to the LVE material model, NLVE BB model is shown to improve the predictions of the experimental results. Thus, the BB model is shown to be useful for adhesives. This will allow designers to perform quantitative FE simulations of adhesive joints.
An embedded compact low-pass filter with parallel coupling and defected ground structure (DGS) is proposed based on the BaTiO3- epoxy composite film. The physical size of the filter is compact due to the slow-wave effect of the DGS. It was embedded into a multi-layered FR-4 packaging substrate through the PCB manufacturing process. The theoretical and experimental results are presented and matched well. The models of embedded filter for different fabrication stages and an equivalent circuit were employed to analyze characteristics of the embedded filter. Theresults indicate that the parasitic capacitance induced by the supporting substrate(prepreg)has a large affect on the properties of the filter.
This paper explores the effectiveness of under-bump comb (UBC) structure to address the capacitive crosstalk couplings in high-speed on-package interconnects applications. Three-dimensional (3D) passive electrical models were established and simulated in this assessment. Transient analyses were conducted to compare the far-end crosstalk (FEXT) profiles and eye diagrams of the UBC and conventional package routing designs. Simulation results shows the UBC design is able to reduce the peak-to-peak FEXT magnitude by >30% at 8Gbps and delivers up-to 20mV/3ps eye margin improvement compared to conventional design. The sensitivity of the UBC design parameters e.g. fin-count and fin-length correspond to electrical performances such as eye diagram opening, signal overshoot and undershoot are also included in this paper for design optimizations.
This paper describes an alternative cross-section sample preparation approach using triple ion beam (TIB) milling to prepare flip chip samples. The 3 cases study results clearly demonstrate the capability and advantages of TIB milling for preparing Lead-free and eutectic C4 solder bumps and back-end-of-line (BEOL) defects as compared to conventional mechanical and Focus Ion Beam (FIB) cross-section.
Despite of numerous advantages of three dimensional integrated circuits (3D-ICs), their commercial success remains limited. The reason lies, in part, on the lack of physical design tools about Through-Silicon-Vias (TSVs) and 3D die stacking. In this paper, we propose a novel TSV placement method on the periphery of the dies. Based on this method, we derive a novel mathematical model to estimate 3D-IC wire-length and area with TSVs before floor-planning. We analyze the impact of TSVs on silicon area and wire-length. A case study with ISCAS benchmark circuits demonstrates that the proposed TSV placement method reduces the chip area and alleviates the reliability issues.
In this paper, electrical measurement and analysis of TSV/RDL is carried out, to evaluate the fabrication process and get a comprehensive understanding of electrical properties of TSV/RDL interconnect structures. DC resistance, leakage current and high frequency characterization are implemented. TSV shows a spreading distribution of DC resistance, with minimum of 4.3 mΩ. Leakage current of TSV reaches 150nA up to 30V without breakdown. Low substrate resistivity lowers the high frequency performance of TSV.
As we move forward to newer silicon technologies requiring finer FC interconnect pitch and packaging solutions with tighter process margins, it is becoming imperative to maximize the benefits of plasma by implementing it prior to UF process. Firstly, key plasma machine parameters were identified, namely plasma processing time, radio frequency (RF) power, gas flow rate and base pressure. Contact angle measurements, UF flow variations and substrate discolorations were used as the output parameters to identify the plasma process window. As part of this study, design of experiments was conducted to identify the critical plasma process parameters for different die sizes. Furthermore, the effect of plasma machine configuration (one with direct vertical plasma mode and the other with horizontal plasma movement for enhanced cavity penetration) was also investigated. The results show that plasma machine configuration play a critical role in uniform spatial contact angle in UF cavity.This paper documents all the evaluations, simulation studies and verification runs done to optimize the plasma process to establish a stable plasma and underfill process, delivering robust FC packages.
Silicone-based adhesive bond separations on polymer and ceramic-based samples were analyzed. Scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX), Fourier transform infra-red spectroscopy (FTIR) and Gas chromatography mass spectrometry (GCMS) analyses were conducted on surfaces of glass fiber reinforced polybutylene terephthalate (PBT) and aluminum nitride samples. Further surface analyses, i.e. surface contact angle measurement, X-ray photoelectron spectroscopy (XPS) and time of flight secondary ion mass spectrometry (TOF-SIMS) indicates that the adhesive bond separation could have been caused by excessive sulfur content on the PBT surface and excessive residual organic compound containing hydroxyl functional group on aluminum nitride surface. Potential separation mechanisms of the adhesive bond for these two case studies were also discussed.
The process of picking large thinned dies, as a crucial step of the pre-assembly part in a 3D integration flow, has been investigated in this paper. Key factors affecting the yield of this process are identified to be the selection of correct collet material, the needle configuration, and ejection height. By combining correct tools and optimized process parameters, large 50 μm thick dies with dimensions up to 31.6×26 mm2 can be successfully picked. Cu and Sn micro-bumps on both sides of the thin dies are well preserved after the picking process.
