This work proposes a unified three-stage framework that produces a quantized DNN with balanced fault and attack robustness. The first stage improves attack resilience via fine-tuning that desensitizes feature representations to small input perturbations. The second stage reinforces fault resilience through fault-aware fine-tuning under simulated bit-flip faults. Finally, a lightweight post-training adjustment integrates quantization to enhance efficiency and further mitigate fault sensitivity without degrading attack resilience. Experiments on ResNet18, VGG16, EfficientNet, and Swin-Tiny in CIFAR-10, CIFAR-100, and GTSRB show consistent gains of up to 10.35% in attack resilience and 12.47% in fault resilience, while maintaining competitive accuracy in quantized networks. The results also highlight an asymmetric interaction in which improvements in fault resilience generally increase resilience to adversarial attacks, whereas enhanced adversarial resilience does not necessarily lead to higher fault resilience.

Single Event Transients (SETs) pose a critical reliability challenge as technology scaling increases sensitivity to ionizing radiation. This paper presents a novel two-stage Machine Learning (ML) framework to predict SET waveforms across diverse gate types, PVT conditions, and process nodes. The methodology first predicts fundamental pulse characteristics, which then serve as features for a secondary model to reconstruct the full temporal waveform. Characterization is performed using bias-dependent SPICE simulations across five technology nodes $(130 \mathrm{~nm}$ to 2 nm). The models demonstrate robust cross-technology generalization. Specifically, the LightGBM-based architecture achieves a Mean Absolute Percentage Error (MAPE) as low as 3.75% on advanced nodes such as IMEC 2 nm. Furthermore, by incorporating a few-shot learning approach, the prediction error is reduced to approximately 2.6%, while only requiring 68.4 seconds on average. This framework enables rapid and scalable SET susceptibility analysis, making it suitable for integration into advanced reliability-aware design flows.

The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while crossbars are optimized for large-scale, highly parallel vector-matrix multiplications (VMMs). In this article, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6 & times; and 19.5 & times; higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks.

The downscaling of VLSI technologies has exacerbated the susceptibility of integrated circuits (ICs) to radiation-induced Single-Event Transients (SETs). This work presents UPSET, a comprehensive and technology-independent EDA framework for probabilistic SET analysis using Static Timing Analysis (STA). Unlike traditional simulation-based methods that suffer from prohibitive runtimes, UPSET leverages graph-based propagation with advanced logical, electrical, and timing-window masking models to evaluate circuit sensitivity efficiently. Key contributions include a novel "Electrical Masking Window" (EMW) criterion that effectively filters non-full-rail pulses early in reconvergent logic and a TimeStamp-based propagation mode that accurately handles complex signal reconvergence with Boolean evaluation. The experimental results over some featured benchmarks demonstrate a speedup of more than 25,000 & times; compared with SPICE while maintaining a tight 4.56% error bound in pulse width estimation. Moreover, experimental validation on 50 benchmarks across varying complexities showcases that EMW enhancement reduces the pessimism to circuit sensitivity by up to 25% on average, providing tighter upper bounds while maintaining scalability to million-gate designs. By integrating seamlessly with standard industrial formats (LEF, DEF, LIB, or SPEF), UPSET enables scalable, accurate soft SET sensitivity assessment for modern digital designs, establishing a robust foundation for automated radiation hardening flows.

Due to the trend towards minimizing guard bands for energy saving purposes, voltage droops are a key limiting factor for the operational frequency of today's VLSI circuits. Adapting clock frequencies dynamically presents the challenge of metastability in the device that detects and stores the existence of voltage droops. We present an implementation of a fast all-digital circuit for adaptive response to droops using the IHP 130 nm process. The description of the design is presented in an accompanying paper. We experimentally validate the functionality of the design on a test chip.

Resilient integrated circuits (ICs) are essential for safety- and mission-critical applications, where hardware faults can result in costly damage or even loss of lives. A resilient IC is designed to detect, tolerate, and adapt in real time to different faulty scanarios, maintaining correct functionality under varying operating and environmental conditions. Specialized sensing and analytics engines embedded in the chip play a central role in resilient ICs by providing real-time insight into the overall state, i.e., "health", of the chip. This paper presents an overview of commonly used on-chip sensors for IC status monitoring, and discusses fundamental design requirements for on-chip processing of sensor-generated data.

The growing computational demands of convolutional neural networks (CNNs) have motivated the use of spectral-domain inference as an alternative to costly spatial-domain convolutions. In this work, we propose a resistive RAM (RRAM)-based spectral-domain convolutional layer that exploits in-memory computing (IMC) for low energy consumption and high parallelism. Both the 2-D Fourier transform and the elementwise multiplications are directly executed on RRAM crossbar arrays, while Hermitian symmetry is leveraged to further enhance the energy efficiency of the transform and subsequent spectral processing. To ensure robustness, the measured RRAM device data are incorporated into system-level simulations to evaluate inference accuracy under the impact of device variability. Furthermore, we introduce a layer-wise mapping framework that adaptively selects between spatial- and spectral-domain execution based on the tradeoff between energy efficiency and accuracy. Simulation results show that the proposed design achieves up to a 2.18 x improvement in energy efficiency across various convolutional layer configurations compared with the spatial-domain design. For VGG-8 on CIFAR-100, the proposed architecture with the layer-wise mapping scheme reduces the energy-delay product (EDP) by 45% while incurring negligible accuracy loss. This work presents the first complete RRAM-based spectral-domain convolutional layer that accounts for device variability, providing a promising solution for edge CNN inference.

Deploying deep neural networks (DNNs) on edge devices requires strong compression with minimal accuracy loss. This paper introduces Mix-and-Match Pruning, a globally guided, layer-wise sparsification framework that leverages sensitivity scores and simple architectural rules to generate diverse, high-quality pruning configurations. The framework addresses a key limitation that different layers and architectures respond differently to pruning, making single-strategy approaches suboptimal. Mix-and-Match derives architecture-aware sparsity ranges, e.g., preserving normalization layers while pruning classifiers more aggressively, and systematically samples these ranges to produce ten strategies per sensitivity signal (magnitude, gradient, or their combination). This eliminates repeated pruning runs while offering deployment-ready accuracy-sparsity trade-offs. Experiments on CNNs and Vision Transformers demonstrate Pareto-optimal results, with Mix-and-Match reducing accuracy degradation on Swin-Tiny by 40

The increasing deployment of AI (artificial intelligence) on edge devices presents major challenges due to strict constraints on computation, memory, energy, and latency. Effective Edge AI systems thus require multi-objective optimization that balances accuracy, hardware efficiency, and reliability. The Horizon Twinning project AIDA4Edge tackles these challenges by developing methods for efficient and reliable AI on resource-constrained platforms. This paper presents key approaches explored within the project, including neural network quantization, hardware-aware neural architecture search, dynamic neural networks, and self-adaptive resilient AI architectures. Finally, these strategies are placed within a broader, biologically inspired paradigm, highlighting neuromorphic computing as a natural continuation of Edge AI efforts toward highly efficient and resilient intelligent systems.

The upcoming 6G communication standard promises unrivaled bandwidth, connectivity, and coverage and will likely span from most remote places over densely populated areas into low earth orbit. The implementation of this vision, however, poses many considerable challenges to the underlying processing hardware with advanced solutions needed to meet these requirements - especially in space. These challenges include the need for significant technological advances, critical demands in terms of performance, reliability, and adaptability, and considerations in terms of the trustworthiness of devices, to name only a few of them. This paper presents our joint efforts to address these needs and enable open-source, adaptive, and fault-tolerant processing systems for 6G communication systems in low-earth orbit.

With the upcoming 6G standard, cellular networks will see an expanded feature set, new use cases, and massive increases in key performance indicators (KPIs) for ultra-reliable low-latency communication (uRLLC) and enhanced mobile broad-band (eMBB). Achieving Tbps-scale data rates with latencies as low as 100 mu s may require rethinking the underlying architecture. Hence, hardware acceleration at all network layers, including the data link layer (DLL), is a promising approach for achieving both high throughput and low latency. We introduce two hardware transmission (TX) buffer designs targeting the DLL of cellular networks, further referred to as SRAM-based design and register array-based (RA-based) design. We discuss their architectures and investigate read, write, and delete latencies, as well as average packet sojourn times under varying ingress rates for designs synthesized with queue counts ranging from 1 to 512, assuming round-robin read access. Our results show mean packet sojourn times as low as 15.554 ns for specific configurations of the RA-based design at 30% of the respective configuration's maximum throughput, peaking at 42.669 mu s when operating at 107.54 Gbps-the maximum throughput of the RA-based design with 512 queues. These findings underscore the potential of DLL-level hardware acceleration in meeting 6G's demanding KPIs.

The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current-voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector-matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments.

In this paper, the gate-level techniques for mitigation of Single Event Transients (SETs) in combinational circuits have been analyzed. The main objective was to compare the SET mitigation techniques in terms of their quantitative impact on SET generation and propagation effects for individual standard cells. The comparison was done with SPICE simulations, using the 130 nm standard cell library. The following SET mitigation techniques have been analyzed: gate upsizing, gate duplication, load upsizing, insertion of transmission gates, insertion of charge sharing logic, insertion of decoupling cells, and insertion of Schmitt trigger. We have shown that the impact of techniques based on insertion of redundant logic depends on the size of added logic and the type of target gate. In addition, we have shown that the most effective SET mitigation in logic circuits can be achieved with a combination of multiple techniques. The obtained results could serve as a guide in selection of SET mitigation approach for a given design.

Simulation-based fault injection is a widely adopted methodology for assessing circuit vulnerability to Single Event Upsets (SEUs); however, its computational cost grows significantly with circuit complexity. To address this limitation, this work introduces an open-source platform that exploits Spatio-Temporal Graph Neural Networks (STGNNs) to accelerate SEU fault simulation. The platform includes three STGNN architectures incorporating advanced components such as Atrous Spatial Pyramid Pooling (ASPP) and attention mechanisms, thereby improving spatio-temporal feature extraction. In addition, SEU fault simulation datasets are constructed from six open-source circuits with varying levels of complexity, providing a comprehensive benchmark for performance evaluation. The predictive capability of the STGNN models is analyzed and compared on these datasets. Moreover, to further investigate the efficiency of the approach, we evaluate the predictive capability of STGNNs across multiple test cases and discuss their generalization capability. The developed platform and datasets are released as open-source to support reproducibility and further research on https://github.com/luli2021/FsimNNs.

The heterogeneous integration of advanced CMOS and emerging technology-based circuits as well as of chiplets at package level present promising avenues to meet the high computational intensity demands of AI applications, in particular due the strict constraints in terms of area, power consumption, and reliability. We classify heterogeneous integration at both the chip level, encompassing novel transistor types such as complementary FETs (CFETs) and novel devices, such as resistive memories, and at the packaging level, spanning from 2.5D to 3D and 5.5D approaches. In this context, the paper presents two case studies assuming the idea of vertical and horizontal integration at chip and packaging level. In more detail, case study I presents the design of vertically integrated inverters based on CFET and thin-film transistor (TFT), as well as the design of SRAM cells based on similar monolitic 3D integrations. In addition, case study II explores the main concepts and the state-of-the-art of heterogeneous integration of chiplets at package level. Quality and reliability aspects that are specific to the heterogeneous integration of advanced CMOS and emerging technologies are further discussed assuming a holistic approach based on circuits’ lifecycle phases. Finally, this paper provides insights and summarizes strategies to address some of these challenges, ensuring high quality and reliable integration for the next-generation of AI hardware.

Reliable electronics plays a major role in shaping our daily lives, being a key enabler for critical applications, such as space missions, avionics, automotive, medicine, banking, automated industry, wireless communication networks, etc. However, design of highly reliable electronic systems remains a challenge with the advances in semiconductor technology and increase in integrated circuit (IC) complexity. In this work, we introduce the Horizon Europe Twinning project TWIN-RELECT, aimed at strengthening the scientific expertise in designing reliable integrated circuits. The paper presents the general project concept and objectives, and main directions of the joint research activities. The primary scientific goal is to contribute to the development of novel, more efficient, European Electronic Design Automation (EDA) tool-chain for design of reliable chips.

Resistive RAM (RRAM) has emerged as a promising non-volatile memory technology for implementing energy-efficient hardware accelerators within the in-memory computing (IMC) paradigm. However, due to the immature fabrication process and inherent material instabilities, frequent read operations during computations can induce read disturb effects, leading to unintended resistance drift and potential data corruption. Existing mitigation approaches primarily focus on detecting read disturb effects and triggering memory refresh operations. In this work, we propose an architecture-level solution that mitigates read disturb in RRAM-based accelerators. Our strategy employs crossbar duplication and decomposes the single high input pulse into two lower-amplitude pulses, effectively minimizing the risk of read disturb. To validate our approach, we develop a simulation framework that incorporates measurement data from characterized RRAM devices under read disturb stress conditions. Experimental results on VGG-8 with CIFAR-10 demonstrate that the proposed method significantly mitigates inference accuracy degradation caused by read disturb in RRAM-based accelerators, while incurring modest area and energy overheads of 12.32% and 2.15%, respectively. This work provides a practical and scalable solution for enhancing the robustness of RRAM-based accelerators in edge and high-performance computing applications.

This work presents HyRPF, a hybrid approach for simulating RRAM-based memory blocks and registers on FPGAs. HyRPF combines the accuracy and speed of physical prototypes with the scalability and cost-effectiveness of computer simulations. Our approach is implemented in the form of advanced IP blocks, which facilitate rapid prototyping of computer architectures that integrate RRAM memory. These blocks are intended to replace existing memory seamlessly, allowing for quick implementation of system designs and tests while also addressing critical challenges such as functional and non-functional device properties. Statistical models are utilized to account for various temporal and non-temporal variabilities and environmental conditions, including temperature influences. Additionally, energy consumption estimates can be conducted. The performance of our approach is validated by simulating register files and caches within a RISC-V processor architecture. The evaluation shows that HyRPF achieves functional accuracy comparable to purely software-based solutions and faithfully reproduces all essential properties of RRAM devices with minimal resource utilization, while outperforming them in terms of simulation speed and achieving a performance faster than real-time. HyRPF has the potential to significantly accelerate the development and testing of RRAM-based systems, providing researchers and engineers with a versatile and easy-to-use tool that balances accuracy and efficiency.

The growing demand for deployment of Artificial Intelligence (AI) on resource-constrained edge devices has motivated extensive research on the design of efficient edge-compatible AI hardware accelerators. One of the most promising solutions are the self-adaptive AI accelerators, capable of optimizing in real time their performance and energy consumption according to application requirements. This work introduces the EU-funded project Twinning for Excellence in Adaptive Edge Artificial Intelligence (AIDA4Edge), aimed to advance the state-of-the-art in the design of adaptive neural network accelerators for edge applications. The main goal is to develop a novel hybrid self-adaptive neural network architecture combining spiking and artificial neural networks, and supporting runtime adaptation of network functionality, precision and reliability. Furthermore, we aim to enhance the neural network training by incorporating hardware and quantization constraints in an automated tuning engine.

The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.