In this work, a novel staggered-gate complementary field-effect transistor (SG-CFET) is proposed to overcome the severe back-end-of-line (BEOL) routing congestion and contact self-blocking issues in conventional CFET designs. The SG-CFET features unique split and staggered gate configuration, which effectively eliminates the requirement for high-aspect-ratio vias and mitigates vertical spatial crowding. The SG-CFET also enables a unique design of SRAM layout that resolving Q-QB spatial conflicts, thereby reducing the standard 6 T-SRAM layout area by 30.26%. The DTCO framework indicate that the optimized routing design effectively reduces critical parasitic RC, achieving 44.14% and 66.31% reductions in storage node (Q-QB) and word-line (Q-WL) coupling capacitances, respectively. Without compromising the static noise margins, the SG-CFET SRAM exhibits significant dynamic performance enhancements, decreasing read and write delays by 8.80% and 16.63%, and the corresponding energy-delay products (EDP) by 22.54% and 30.36%, respectively. These results fully validate the SG-CFET as a highly promising architecture for continuous area scaling and high-performance digital circuit applications.
Edge computing and always-on intelligent systems impose growing demands for high-density and low-power embedded memories. Voltage-controlled magnetic anisotropy magnetic random-access memory (VCMA-MRAM) is a promising candidate due to its sub-nanosecond and energy-efficient write operation. Conventional VCMA-MRAM adopts a source-line (SL)-write scheme to suppress unselected bit-cell write disturbance, but it requires a boosted word-line (WL) voltage to ensure sufficient write margin. To address this issue, this paper proposes a bit-line (BL)-write VCMA-MRAM architecture that eliminates the need for WL voltage boosting and uses a BL standby biasing scheme to suppress write disturbance. Specifically, the BL standby bias is set to half of the write voltage, which reduces the peak parasitic pulse across unselected magnetic tunnel junctions (MTJs). Under the evaluated conditions, this voltage level does not induce unintended switching, enabling reliable BL writing while reducing the WL voltage by 33.33% compared with the conventional SL-write scheme. Furthermore, the optimized BL-write architecture reduces the bit-cell area by 41.67% owing to the simplified interconnection between MTJs and transistors and the grounded-SL layout. Additionally, the optimized BL-write architecture, together with the proposed BL standby biasing scheme, reduces the write and read energies by 61.27% and 61.00%, respectively. The proposed VCMA-MRAM design also supports reconfigurable physically unclonable function (PUF) operation through long-pulse stochastic switching without additional dedicated PUF cells, reducing the reconfiguration energy by 80.65%.
HfO2-based ferroelectric films are promising for next-generation nonvolatile memory due to their excellent CMOS compatibility. However, the severe imprint effect remains a key reliability issue of the films. In this work, a controllable WOx interlayer was introduced into W/WOx/HfZrO2/W ferroelectric capacitors by O2 plasma oxidation of the tungsten film. The effects of WOx interlayer on polarization, endurance, and imprint characteristics of the capacitor devices are systematically investigated. The optimized device exhibits an increase in 2Pr from 33 to 45 μC/cm2 and an endurance improvement to 108 cycles. Imprint measurements show that the WOx interlayer could effectively suppress the P–V loop shift, especially at high temperature, reducing the shift by 41%. The results of this study demonstrate that WOx interfacial engineering, acting as both an interfacial buffer and an oxygen reservoir, effectively improves the imprint behavior and reliability of HfO2-based ferroelectric devices.
Amorphous oxide defects in MoS2/high-kappa gate stacks cause severe reliability issues such as hysteresis and bias-temperature instabilities (BTI), hindering 2D field-effect transistors (FETs) from achieving Si-standard reliability. While existing studies primarily focus on the energetic alignment between oxide defect bands and the channel conduction band edge, the role of the van der Waals (vdW) gap as a defining feature of 2D interfaces remains underexplored. Here, by performing TCAD simulations on scaled top-gated MoS2/HfO2 FETs with border oxide traps, we reveal that the vdW gap plays a dual role in charge trapping dynamics. For deep traps, it eliminates contact-induced band bending, suppressing pre-filling and enabling faster trapping at high gate bias. For shallow traps, it introduces a tunneling barrier that slows charge trapping and suppresses emission to the gate by limiting the downward shift of the gate Fermi level, thereby increasing hysteresis. Consequently, the bias stability of nanoscale MoS2 FETs is governed not only by the energetic alignment of defect bands but also by the vdW gap as a non-negligible factor. These findings provide critical insights for the reliability-aware design of future 2D electronics with proper consideration of the vdW gap.
Line width roughness (LWR) and hot-carrier degradation (HCD) pose critical challenges to the advancement of nanoscale complementary metal oxide semiconductor (CMOS) technology. The correlation between gate \ active area (AA) LWR and HCD-induced variability remains insufficiently explored. This work studies LWR-driven variability of HCD in CMOS devices. The experimental results show that reductions of 1.81 nm in active area LWR and 1.16 nm in gate LWR decrease hot carrier degradation variation by 18.6% and 34.7%, respectively. Moreover, mechanistic insights from combined electrical characterization and simulations, reveal that gate LWR leads to non-uniform doping and electric-field distribution in the channel, increasing local carrier temperature and interface-trap density. Whereas AA LWR modifies the potential barrier in the space-charge region near the channel boundary and enhances the local electric field and carrier concentration along the channel edge. Furthermore, by reducing both AA and gate LWR, barrier fluctuation along the junction line can be suppressed, thereby alleviating HCD-induced current-onset voltage variability. This work demonstrates that optimizing AA and gate LWR is essential for enhancing the reliability and variability of nanoscale MOSFETs and integrated circuits.
