Abstract This paper presents a novel device-level approach for controlling the temperature effect inversion (TEI) phenomenon in saddle metal–oxide–semiconductor field-effect transistors (MOSFETs). Previous studies on TEI have primarily focused on circuit-level compensation techniques, while systematic investigations from a device-structural perspective remain limited. In this work, the impact of key structural parameters of saddle MOSFETs on temperature-dependent propagation delay characteristics is analyzed. Technology computer-aided design simulation results demonstrate that structural modifications can effectively regulate delay inversion behavior in the subthreshold region. Device-level control of TEI directly influences both the propagation delay and the TEI operating range (TEI OR ) of circuits. By varying structural parameters, including recess depth, gate width, and side depth, both the TEI OR and the propagation-delay utilization range can be expanded. Among these parameters, gate width exhibits the highest effectiveness, increasing the TEI OR by up to 33%. These results indicate that TEI can be actively controlled through device structural engineering rather than relying solely on circuit-level techniques, providing valuable design guidelines for temperature-adaptive and thermally adaptive and TEI-aware digital complementary metal–oxide–semiconductor circuit applications.
Abstract Two-dimensional semiconductors and ferroelectrics offer complementary routes to scaled electrostatic control and embedded nonvolatility. This work evaluates an asymmetric dual-gate ferroelectric heterostructure field-effect transistor that combines a monolayer MoSi 2 N 4 channel, an α -In 2 Se 3 ferroelectric top-gate layer and an h-BN bottom gate. The framework couples a Landau–Ginzburg–Devonshire description anchored to reported α -In 2 Se 3 polarization, coercive-field and permittivity data, including depolarization, coercive-field thickness scaling and Curie–Weiss temperature dependence, to a two-dimensional finite-volume electrostatic solution of the gate stack and a charge-based transport kernel with velocity saturation. The spatial solution shows that a 6 nm ferroelectric over a 12 nm gate permits strong drain-field fringing through the high-permittivity layer, and that a 1 nm h-BN bottom gate removes most of the top-gate control. A design criterion fixed in advance (SS ⩽ 75 mV dec − 1 , DIBL ⩽ 50 mV V − 1 , retained bottom-gate threshold tuning) selects a 2.5 nm ferroelectric and a 10 nm h-BN bottom dielectric at L G = 12 nm, giving SS = 71.4 mV dec − 1 , DIBL = 45.7 mV V − 1 , I ON = 341 μ A/ μ m, an ON/OFF ratio of 3.5 × 10 7 and a 0.11-V memory window at V DD = 0.7 V. The ferroelectric thickness does not show an intrinsic optimum: swing and DIBL degrade monotonically with thickness while the memory window increases, so the design point is a constrained optimum whose location moves between 2.25 and 3.5 nm across ten literature-based parameter sets. A factorial comparison shows that high-permittivity gating and the second gate are sub-additive in drain-field screening, and a decomposition attributes the swing to thermionic, bottom-gate, short-channel and interface-trap terms. Temperature, interface-trap, contact and variability analyses define the conditions under which the stack is useful, and a comparison with a published sub-10 nm MoS 2 FET, which agrees in order of magnitude and trend but not quantitatively, indicates the accuracy limits of the short-channel predictions.
Abstract This work presents a comprehensive numerical investigation of bismuth oxyselenide (Bi 2 O 2 Se) as a standalone absorber material for high-efficiency single-junction solar cells using SCAPS-1D simulation. The proposed device architecture with a structure ofFTO/TiO 2 /Bi 2 O 2 Se/Cu 2 O/Ni was optimized by independently varying key material parameters, including absorber thickness, band gap, donor concentration, and defect density. Additional performance parameters were evaluated by varying the series and shunt resistances, operating temperature, and back-contact work function. Furthermore, a band alignment analysis was conducted to elucidate interfacial charge transport mechanisms and ensure a realistic device assessment. The band gap of Bi 2 O 2 Se was varied within 1.0–1.6 eV, alongsideindependent optimization of the absorber thickness, allowing precise control over the photovoltaic response. In-depth electrical analyses—comprising capacitance–voltage, Mott–Schottky characteristics, frequency-dependent capacitance, conductance response, Nyquist impedance, generation–recombination dynamics, and electron–hole current density distribution—confirmed efficient charge separation, favorable transport across the device interfaces, and suppressed recombination within the proposed device. The optimized configuration featuring a band gap of 1.4 eV and an absorber thickness of 600 nm exhibits a remarkable power conversion efficiency (PCE) of 26.03%, with J SC = 30.15 mA cm −2 , V OC = 1.05 V, and fill factor = 81.63%. These results unveil Bi 2 O 2 Se as a promising next-generation absorber material with strong optoelectronic potential, offering a pathway toward efficient, stable, and environmentally benign photovoltaic technologies.
Abstract A direct coupling methodology between Geant4 and SCAPS-1D is introduced for the accurate simulation of betavoltaic devices, and validated against experimental photovoltaic measurements on GaAs/AlGaAs heterostructures. Unlike conventional approaches that rely on empirical fitting functions for the carrier generation profile, the present work computes the depth-dependent energy deposition of a 63 Ni beta source directly using Geant4 with the Penelope low-energy physics constructor, converts the result to a volumetric electron–hole pair generation rate via the Klein relation, and imports it into SCAPS-1D as a user-defined profile. Six-layer and five-layer GaAs/AlGaAs n–p and p–n configurations are characterized under both AM1.5 G illumination and 63 Ni irradiation. Simulated photovoltaic parameters show good agreement with experiment for both junction polarities. Under betavoltaic operation, the n–p structures maintain a consistent relative efficiency advantage of approximately 9% over the p–n structures when bulk SRH defects are present, whereas for defect-free material the polarity difference lies within the parameter-set uncertainty. Removal of the heavily doped front GaAs cap layer improves betavoltaic efficiency by 54%–62% by eliminating parasitic absorption in the surface-peaked beta deposition region. Bulk SRH defects reduce efficiency by approximately 47–53%. Shunt resistance ( R sh ) is identified as a critical design parameter: at nA cm −2 current densities, R sh ≫ 20 MΩ·cm 2 is required to avoid severe fill factor degradation. Among the investigated structures, the defect-free n–p five-layer configuration achieved the highest simulated efficiency of 2.84% under 13.87 mCi cm −2 63 Ni irradiation. A controlled sensitivity study using conventional bulk-GaAs effective densities of states ( N c = 4.21–4.70 × 10 17 cm −3 ) confirms that the cap-removal and defect conclusions are insensitive to this parameter choice, changing the maximum efficiency only marginally (from 2.84% to 2.82%), while lowering the open-circuit voltage of the defect-containing devices by 37–40 mV. The methodology provides a physically consistent framework for heterostructure betavoltaic device design and optimization.
Abstract Understanding the origin of bias-stress instability is critical for the reliable operation of amorphous In–Ga–Zn–O (IGZO) thin-film transistors (TFTs). Here, we investigate the mechanism of positive bias stress (PBS)-induced threshold-voltage ( V th ) shifts in bottom-gate IGZO TFTs through electrical, chemical, and electronic structural analyses. The devices exhibit typical n-type characteristics with a field-effect mobility of 5.2 cm 2 /V∙s and an on/off ratio exceeding 10 4 . Under PBS, a significant positive V th shift is observed, whereas the mobility and subthreshold swing remain nearly unchanged. X-ray photoelectron spectroscopy and density-of-states analyses reveal no detectable changes in the chemical states or electronic structure of the IGZO layer after PBS. In contrast, frequency-dependent capacitance measurements show a reduced resonance frequency and increased trap density in the SiO 2 dielectric. These results indicate that dielectric electron trapping, rather than semiconductor degradation, is the dominant origin of PBS-induced V th shifts in IGZO TFTs.
