Colloidal quantum dot light-emitting diodes (QLEDs), featuring emissions with narrow full width at half maximum (FWHM) emission and solution processability, are promising candidates for high-resolution microdisplays. However, integration of silicon-based complementary metal-oxide-semiconductor (CMOS)-driven QLEDs at ultra-high pixel densities remains fundamentally limited by inefficient hole injection and severe surface nonplanarity of the silicon-based CMOS backplane. Here, interfacial work-function engineering is employed to concurrently mitigate the hole injection barrier and improve the backplane surface. Specifically, an indium tin oxide (ITO) interlayer is inserted between the TiN electrode of the CMOS backplane and the PEDOT:PSS hole injection layer, thereby improving energy-level alignment and smoothing interfacial morphology. Consequently, for the first time, a silicon-based CMOS-driven QLED microdisplay is demonstrated with an ultra-high pixel density of 11000 pixels per inch (PPI), a high resolution of 3840 × 2160, and a peak brightness of 29789 cd/m2. To the best of our knowledge, this represents the highest PPI reported to date for a silicon-based, CMOS-driven QLED microdisplay — establishing a viable technological pathway toward ultra-high-resolution emerging near-eye displays.
In this work, we demonstrate atomic-layer-deposited (ALD) indium oxide (In2O3) power transistors with scaled channel length and offset region. Low specific on-resistance (Ron,sp) of 0.034 mΩ·cm2, high breakdown voltage (VBD) of 350 V, and a record-high Baliga’s figure of merit (BFOM) of 3.6 GW/cm2 are achieved. It is understood that the breakdown mechanism of In2O3 differs from that of conventional semiconductor power transistors. The band-tail states in the subgap capture impact-ionization-generated electrons and suppress mobile hole generation, thereby inhibiting carrier multiplication and hole trapping. Consequently, effective breakdown electric field of In2O3 over 17.2 MV/cm is demonstrated, exceeding those of common wide bandgap semiconductors such as SiC, GaN, etc.
Using the newly developed integrated process, n-type body-contacted vertical-channel FETs (BC-VFETs) were successfully fabricated, achieving low off leakage and wide threshold-voltage adjustability. It was confirmed that the body-contact position, length of upper/lower gate could be accurately controlled by epitaxial growth, which are crucial for massive manufacturing. The horizontal p+ body is formed by the dopant diffusion in epitaxial doped side layer. The metal gate etch-back minimizes parasitic gate-drain capacitances. In transfer measurements, applying a grounded body bias reduces minimum off-state current (Imin) to 73% of the floating-body value, while a –0.5 V bias further suppresses it to 44%. A Vt shift of –0.38 V/V is also achieved as VB is swept from –1 V to 0 V. Four-terminal analysis confirms that gate-induced drain leakage (GIDL) dominates the deep off-state, while e-BTBT at the body depletion boundary overtakes the body-bias-induced suppression of channel off-state leakage under deep negative body bias, introducing a fundamental trade-off to the VB setting. With further scaling, this architecture offers a viable path toward 4F2 DRAM integration.
