A relaxation oscillator(RO) composed of a voltage and current reference (VCR) and a digital current comparator is presented in this paper. By using two different types of resistors with opposite temperature coefficient (TC) in the VCR, this design successfully stabilizes the operation frequency from -20 to 100° C with a very simple structure. Designed in a standard 180nm CMOS process, the proposed RO consumes 120nW under a 0.8V supply and operates at 121kHz, with a TC as low as 36.2 ppm/°C.
A relaxation oscillator(RO) composed of a voltage and current reference (VCR) and a digital current comparator is presented in this paper. By using two different types of resistors with opposite temperature coefficient (TC) in the VCR, this design successfully stabilizes the operation frequency from -20 to 100° C with a very simple structure. Designed in a standard 180nm CMOS process, the proposed RO consumes 120nW under a 0.8V supply and operates at 121kHz, with a TC as low as 36.2 ppm/°C.
Neural Processing Unit (NPU) has become the state-of-the-art solution for accelerating artificial neural networks and is increasingly integrated on the System-on-Chip (SoC) of edge devices such as smartphones and cameras. However, adopting NPU in mission-critical systems, such as aerospace aircraft and autonomous driving demands high reliability, which is currently less explored on industrial NPUs. In this work, we target one of the critical reliability issues - permanent fault - for modern NPUs and provide an instruction-driven fault detection method named LIPFD-NPU. The approach executes dedicated network instructions in a self-testing fashion and generates fine-grained information on the potential fault's location, type and level of impact. An FPGA-based fault emulation framework is used to verify LIPFD-NPU. The results indicate that LIPFD-NPU effectively detects faults with tiny overheads of 0.2% in silicon area and 0.5% in power consumption.
With the rapid growth of data centers, the power supply has shifted from 48/12/1V two-stage architecture to 48/1V single-stage. In this paper, a new two-phase sawtooth voltage mode PWM control is proposed for the double step-down (DSD) converter. In order to solve the problem of inherent cycle delay of PWM control, a fast-transient response scheme is proposed. The converter also has a precharge and soft start scheme, which is designed with a 0.18 µm BCD process. It achieves peak efficiencies of 92.7 % , 90%, 87.8%, and 86% at 250 kHz, 500 kHz, 750 kHz, and 1 MHz, respectively. During a 1A/10 ns load jump, the undershoot is reduced from 200 mV to 102 mV and the setting time is reduced from 5.3 µs to 1.6 µs.
Instruction set randomization has been proposed for many years as a strategy against code injection. However, most of the methods are based entirely on software, which is vulnerable to possible threats like key leakage or bypassing attack. The translation of instructions also brings the loss of performance. Some designs randomize the instruction set based on hardware, but using weak approaches which can be easily bypassed. In this paper, we propose a hybrid instruction set randomization with both compiler support and hardware extension on a RISC-V processor. We adopt AES-128 to randomize RISC-V instruction set with little performance loss. The design has been implemented on Xilinx AV7K325 FPGA board, the results shows that RISC-V instruction set is randomized with no changes in clock frequency, 1377 LUTs increase in resources and 0.38% performance overhead.
