Division operation is necessary for many applications, especially optimization algorithms for machine learning. Usually, a certain degree of loss is acceptable in calculating nonsignificant intermediate variables for a considerable speed improvement. This paper proposes a specialized divider to accelerate machine learning optimization algorithm implementation on hardware. Inspired by the fast inverse square root algorithm, we designed a hardware implementation method according to the algorithm, which generates an approximate division result with conversion between floating-point and fixed-point numbers and multiplication. This paper includes three versions of divider: fastDiv accuracy, a conventional design with a 35% less delay and minimal error compared to delay-minimized standard divider from the Synopsys DesignWare library; fastDiv area, an area-oriented design with a 67% less delay and acceptable error compared to the standard divider constrained to the same area size; fastDiv speed, the fastest design with a 54% less delay compared to delay-minimized standard divider. All these three versions can be applied in deploying optimization algorithms in FPGA or ASIC design on demand.
This paper presents a 12/10/8/6-bit successive approximation register (SAR) analog-to-digital converter (ADC) which is compatible with single-ended mode with only one set of SAR logic. Oversampling, dithering and dynamic element matching (DEM) techniques are combined to increase both SNR and linearity to extend accuracy. The proposed ADC is implemented in a 110nm CMOS technology and the total area is 0.194mm 2 • At 1MS/s and VREF=3.3V, ENOB is 11.05b, SFDR is 89.91dB when the input amplitude is 2.97V (-1dBFS) while consuming 742.6uW. The application of DEM helps improve the SFDR by about 4dB. The measured DNL and INL are +/-0.65LSB and +/-1.14LSB respectively. At an oversampling ratio (OSR) of 64, the SAR ADC achieves the ENOB of 13.5b and dither helps improve the absolute accuracy of the DC signal.
This paper presents a V-band low noise amplifier (LNA) implemented in a $\boldsymbol{0.15-\mu} \mathbf{m}$ Gallium Arsenide (GaAs) pseudomorphic high electron-mobility transistor (pHEMT) technology. The LNA adopts a three-stage common-source (CS) topology. Each transistor has a bias circuit, and the microstrip-line inductor is used to realize the input noise matching network, the interstage, and the output matching network. Circuit simulations show that our LNA scores a 12.87-dB small-signal gain, the 3-dB bandwidth ranges from 60 GHz to 66 GHz, and the current consumption is 30 mA under a 5-V supply voltage. Its noise figure is 5.9 dB, and the output 1-dB compression point is 10.5 dBm. The chip area is $\boldsymbol{1.32}\times \boldsymbol{1.5}\mathbf{mm}^{2}$ .
A phase shifter is widely used in the phased array radar system and multi-beam antennas, which enables phased arrays for beam scanning by changing the phase of the corresponding radiating element. Based on GaAs $\boldsymbol{0.15}\mu \mathbf{m}$ process, this work researches and designs a 32-38GHz 6-bit phase shifter, in which the overall size of the chip is 1.87 mm $\times 1.5$ mm. The proposed phase shifter is designed using high and low pass filter types for $\boldsymbol{180}^{\circ}$ and $\boldsymbol{90}^{\circ}$ units. In order to alleviate the problem of too-large inductance and too-small capacitance, this work uses Low-pass and bypass filter types for $\boldsymbol{45}^{\circ}, \boldsymbol{22.5}^{\circ}\boldsymbol{11.25}^{\circ}$ , and $\boldsymbol{5.625}^\circ$ units. The RMS phase shift error of this 6-bit phase shifter is less than $\boldsymbol{4}^{\circ}$ .
Dry electrode interface provides convenient means for continuous biopotential recording, however it requires front-ends with high input impedance to maintain high SNR. This paper proposes a mode change calibration loop (MCCL) for automated input impedance enhancement of capacitively-coupled instrumentation amplifiers (CCIA). To compensate all parasitic capacitors seen at the input nodes which limit the input impedance performance, the MCCL precisely adjusts positive feedback capacitors and automatically converges towards the ideal value. Active shielding is also integrated for cancelling parasitic capacitors outside the chip. Implemented in a typical $\boldsymbol{0.18}-\mu \mathbf{m}$ CMOS process, the post simulation result shows that the front-end consumes $\boldsymbol{4}\ \mu\mathbf{A}$ and achieves $\boldsymbol{1.8}\ \mu\mathbf{V}$ rms input-referred noise over 0.5-100 Hz. After calibration, $\boldsymbol{20}\ \mathbf{G}\Omega$ input impedance at 50 Hz was achieved.
