In MOSFETs, mobility enhancement is a key factor for improving the electrical performance and enabling their use in new applications, such as low-power, digital, and medical applications. This mobility improvement can be technically achieved by using different techniques that exploit the complex behavior of mobility (Coulomb, phonon, and surface roughness mobilities). Previous reviews have primarily focused on two main technologies: the introduction of mechanical stress and crystallographic orientation. Therefore, this review summarizes all key techniques that can enhance mobility, and each of these techniques is linked to a physical origin. Mechanical stress notably affects phonon mobility, whereas silicon thickness and channel impurities mainly affect the Coulomb mobility. Moreover, the dielectric oxide type, heat treatments, surface cleaning, ionic implantation in the oxide, and oxynitrides affect surface roughness mobility. In addition, the crystallographic orientation affects Coulomb, phonon, and surface roughness mobilities. Furthermore, the study of the series resistance engineering also affects the performance. Therefore, the simultaneous use of multiple of these techniques leads to an enhancement of the effective mobility at low, medium, and high effective electric fields, and the combined effect results in a more significant mobility increase.

RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, integration has driven the wireless business to achieve appropriate cost and form factor, and CMOS Silicon-on-Insulator (SOI) was adopted about 10 years ago and is now the dominant technology for Radio Frequency Switches (RF SW) in RF FEMs for cell phones and Wi-Fi [1]. While RF SW performances integrated on RF SOI technologies have exceeded what was feasible using GaAs technologies, 6G systems require even more stringent performances and consequently RF SOI technologies must continue to be improved. In this paper, the optimization of an advanced 200 mm RF SOI technology, which achieves a record $R_{\text{on}} \times C_{\text{off}}$ of 60 fs by introducing 65 nm gate length at the Front End of the Line (FEOL) to reduce the channel resistance, is proposed and discussed. Furthermore, an innovative air gap process option at the Back End of the Line (BEOL) is proposed to achieve parasitic capacitance reduction.

As the demands of RF applications are rising, optimization of internal MOSFETs capacitances is a key issue to improve the cut-off frequency. In this abstract we report the development of a novel N-MOS architecture processed on 8-inch SOI wafers. This architecture has a gate oxide with variable thickness along the channel and a reduced bottom gate length aiming at minimizing Gate to Drain/Source capacitance (1) (2). This improvement on Gate to Drain/Source capacitance mainly comes from a decrease in overlap capacitances as described in (3). The new process flow is composed as usual until Poly-Si gate etching. By controlling the species flow and process time during plasma etching steps, over etch at the bottom of the gate is performed (fig.1(a,b)). Poly-Si gate notching engineering is possible due to reduction of the passivation layer thickness at the bottom of the gate during plasma etch. As described in (4) the gate is first etched using a HBr/CL2/O2 chemistry until reaching close to the bottom of the gate, allowing the formation of a passivation layer made of SiOxCly and the anisotropy of the etch. To etch the remaining thickness HBr flow is augmented while CL2 and O2 flow are reduced, preventing formation of passivation layer. This leads to isotropic etch of the bottom gate and reduction of the gate length as regard to the top Poly-Si dimension. This over-etch reduces the physical gate length without changing the effective and the on-mask gate lengths, leading to overlap capacitance reduction. To produce gate oxide with variable thickness under gate sidewalls a two-steps process is performed. First, full plate oxide is grown before poly-Si deposition to act as middle gate thickness. Then undercut is performed, consisting of lateral etching of the gate oxide under gate sidewall after gate etch (fig.2.a). To achieve this undercut, hydrofluoric acid (HF) wet etch has been chosen. First trials with very low HF concentration become quickly saturated leading to small lengths under gate sidewalls (fig.2.b). Then more acidic solutions were used allowing satisfying undercut lengths (fig.2.c). Finally rapid thermal oxidation (RTO) is performed to obtain an oxide bird beak at both gate side as both Poly-Si gate and Si from the active region react with ambient O2 in the chamber. This leads to a gate oxide with variable thickness along the channel (fig.3(a.b)) which has both effects: to get smoother poly-Si foot and a down step in the active between channel and Source/Drain regions. During this process step, a built-in spacer on the gate sides for LDD implantation is formed. RTO process step has grown a thicker oxide over Source/Drain areas which has to be reduced to allow an accurate LDD implantation, this is done by anisotropic etching. After these new steps, the process goes back to a standard N-MOS process flow. Some early versions of the notched gate have been investigated (5), and these experiments and details on processing recipe seem promising for electrical results. As poly-Si foot has been smoothed and graded gate oxide (GGO) on top of overlaps region is formed. It would allow a reduction in parasitic capacitances improving cut-off frequency of RF applications. References RF LDMOSFET with Graded Gate Structure. Xu Shuming, Foo Pan Dow. Toronto : s.n., 2001. 1th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings. pp. 221-224. DOI:10.1109. Notched-Gate pMOSFET with ALD TiN/High-κ Gate Stack Formed by Selective Wet Etching. Zhang, D. Wu and J. Lu and P.-E. Hellström and M. Östling and S.-L. s.l. : The Electrochemical Society, Inc., 2004, Electrochemical and Solid-State Letters, Vol. 7, p. 228. 10.1149/1.1795612. A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs. Fabien Pregaldiny, Christophe Lallement,Daniel Mathiot. s.l. : Solid State Electronics, 2002, Vol. 46, pp. 2191–2198. https://doi.org/10.1016/S0038-1101(02)00248-4. Design of notched gate processes in high density plasmas. J. Foucher, G. Cunge, L. Vallier, and O. Joubert. s.l. : AVS: Science & Technology of Materials, Interfaces, and Processing, 2002, Vols. Journal of Vacuum Science & Technology B 20,. http://dx.doi.org/10.1116/1.1505959. Notched gate MOSFET for capacitance reduction in RF SOI technology. al, L. Antunes et. s.l. : 2023 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS), 2023. doi: 10.1109/DTTIS59576.2023.10348288. Figure 1

Because of its role in circuit switching speed, the ON-state (I ON ) current is one of the most important parameters of MOSFET devices. Several design or technological process enhancements can increase the I ON current and one of them is to incorporate a tensile layer in the MOSFET process to constrain the channel and obtain better electron mobility. In this paper, we present how a source/drain recess can lead to a better efficiency of the tensile layer.

In this paper, we discuss a new development of 40nm SONOS eSTM™ (embedded Select in Trench Memory). We present an experimental study based on hot carrier injection mechanism for both programming/erase operations, performed on this new eNVM architecture. The optimization of drain and select gate biases, in order to define the programming and erasing threshold voltages, is also detailed. All the characterizations have been carried out for two different SONOS eSTM™ architectures giving an opportunity to propose different solutions. One of this using a continuous silicon nitride layer for two neighbour cells, taking advantage on the discrete charge trapping nature. As well, we performed endurance tests up to one million cycles for both architectures to evaluate the memory endurance.

Reduction of parasitic front-end capacitance is one of the key factors to improve the performance of RF applications. In this work, we report the development of an atypical gate architecture allowing the reduction of the source/drain overlap capacitances of a PD-SOI n-MOS transistor. After presenting the process flow and monitoring methods, we discuss the low frequency and RF electrical results such as C OFF , R ON , RF Vmax .

In this work, ring oscillator test structures are designed and characterized to evaluate the in-circuit performance of a new medium-voltage (around 2-5 V) transistor architecture developed via process optimization in a 40 nm embedded non-volatile memory (eNVM) CMOS technology. The transistor is zero-cost in terms of photomask and process steps. It is compared to an existing transistor available in the technology. A SPICE model (Simulation Program with Integrated Circuit Emphasis) of the new device is developed to evaluate its circuit-level performance through electrical simulations. The simulation results are complemented by experimental results, and both show a large increase in the ring oscillator frequency for the new transistor, compared to the existing one. In addition, the reliability of the new transistor is evaluated at the device level with hot-carrier injection (HCI) stress tests and at the circuit level with power-supply stress tests.

Schmitt triggers are useful circuits in analog and digital domains, and they can be used to highlight the strengths and weaknesses of their constituent transistors. In this paper, a benchmark of a new zero-cost (in terms of process steps) medium-voltage transistor build via process optimization is performed in a 40 nm CMOS low-cost technology using Schmitt triggers. The process optimization lowers the threshold voltage, increases the ON-state current at the cost of increasing the OFF-state leakage current and the gate oxide capacitance. A circuit-level study is conducted to see how these characteristics translate into the performance of a Schmitt trigger. Measurements show a good correlation between the transistor-level performance and Schmitt trigger figures of merit.

In this paper, the reliability of thick SiO2 gate oxides is assessed using quasi-static and multi-frequency capacitance measurements after constant current stress. A comprehensive study of oxide wear-out is presented, highlighting trapping mechanisms and switching states generation occurring during stress at high electric fields. Measurements are performed on furnace grown and HTO-based oxides and the correlation with lifetimes extrapolated from time-dependent dielectric breakdown is discussed.

The reliability requirements of Flash memory become more and more challenging. Flash memory technology development needs test chips to allow large statistical studies and a product-like approach. In this paper, we present a methodology of bitmap analysis to extract and follow the intrinsic and extrinsic parameters of a 40nm eFlash technology during ramp-up. This methodology is, first, based on analog bitmap acquisition on 512kB test chip, followed by correction of spatial variabilities like peripheral circuits' influences, array organization impacts and process-induced effects, to extract supplementary cell electrical parameters such as threshold voltage, transconductance or programing window. Finally, such an analysis tool enhances the advantageous properties of a test chip, its large memory cell statistics and its product-like organization, to give more reliable data. It yields more information about intrinsic cell technology weaknesses and the best way to tackle them when integrated at product level.

Ce papier décrit le développement des prochaines générations de mémoires non volatiles (NVM). Ce travail se focalise dans un premier temps sur un rappel des technologies mémoires embarquées dites classiques, intervenant sur de nombreuses applications à base de microcontrôleurs. L’accroissement de ce champ d’applications engendre le respect de nombreux critères (ultra basse consommation, augmentation de puissance, etc.) nécessitant une évolution technologique vers des noeuds avancés comme le 40nm et le 28nm. Un état de l’art des architectures actuelles permettra alors de découvrir les différentes technologies existantes et de comprendre les procédés utilisés. Nous aborderons d’abord les notions théoriques utilisées, puis les freins potentiels à anticiper dans cette génération de mémoire et ses possibles améliorations.

The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a 512kB test chip with a lower annealing temperature. This result can be linked with the decrease of nitrogen in the bulk oxide, improving oxide wear out performance against electrical stress and stress induced leakage current (SILC). The on-chip characterization is, here, an invaluable tool to show the extrinsic behavior in the memory array and apply product-like stress.

Targeting the integration of embedded non-volatile memories on thin-silicon body technology, high temperature oxide (HTO) is evaluated on a 40nm automotive eFlash process as replacement of furnace grown thick gate oxide for high voltage transistors. Different thermal treatments are evaluated to enhance HTO quality, including growth of interfacial layer, reoxidation and high temperature annealings. Transistor performance and reliability are thoroughly studied, showing that the main challenge for HTO integration is time-dependent dielectric breakdown. Because of higher charge trapping, HTO is found to be less reliable than grown oxide. However, optimized dedicated treatments successfully improve HTO quality and reliability.

This paper presents the performance and reliability evaluation of high voltage MOS gate stacks integrated in an advanced CMOS technology platform. The aim of this study is to evaluate the compatibility of a thick silicon dioxide with a high-k metal gate stack which replaces the standard polysilicon gate. Using capacitors, physical, electrical, and reliability characterizations are carried out and TiN metal gate is found to be a potential issue as it induces a high density of interfacial traps. Despite these traps, oxide lifetime could still meet demanding requirements. Thus, using the high-k metal gate stack on top of a thick SiO2 gate oxide could be a potential solution for high voltage transistors integration on advanced CMOS platforms with embedded non-volatile memories.

The present paper proposes to investigate the effect of short pulsed Program/Erase signals on the functioning of Flash memory transistors. Usually, electrical operations related to said devices involve the application of single long pulses to various terminals of the transistor to induce various tunneling effects allowing the variation of the floating gate charge. According to the literature, the oxide degradation occurring after a number of electrical operations, leading to loss of performance and reliability, can be reduced by replacing DC stress by AC stress or by reducing the time spent under polarization by the MOS-based devices. After a brief presentation of the functioning of the Flash memory transistors tested in this work, the experimental setup used to replace standard electric signals with short pulses will be described. Electrical results showing the benefits of programming and erasing non-volatile memories with short pulses will then be presented.

This paper presents an original solution to decrease significantly the power consumption of CMOS digital circuits. The supply voltage VDD and the MOSFET width are reduced and allow lowering the dynamic current of circuits by 25%. A CAD-to-mask script was developed in order to automatically reduce all physical widths of low-voltage transistors used in standard cells. With this operation, no additional redesign of standard cells was necessary. Moreover, a new optimized process based on e-NVM (embedded Non-Volatile Memory) CMOS 80 nm technology is developed. ION current is improved by 15% and 50% for NMOS and PMOS transistors, respectively. This, let us decrease dynamic current without impacting circuit performance. Finally, the static current of the circuit is reduced by 60% through design and process optimization.

This paper describes different solutions to decrease dynamic consumption of circuits processed on an embedded non-volatile memories CMOS 80 nm technology. Up to 25 % in dynamic power reduction is demonstrated without degrading performances and static leakages of devices and above all, with full DMR compliancy. Ring oscillator designs are used to estimate the dynamic power gain, comparing new development process (B) to reference process (A) currently in use in manufacturing.

A new experimental setup used to perform non-destructive measurement of electrical quantities on semiconductor devices is described in this paper. The particular case of tunneling current measurement in n-type semiconductor-oxide-semiconductor (SOS) capacitors, whose dielectrics play a crucial role in non-volatile memories, has been investigated. When the gates of such devices are polarized with a sufficient bias voltage while the other terminals are grounded, tunnel conduction of electrons through the thin oxide layer is allowed. Typical tunneling current measurements obtained with this advanced setup are presented and compared to the results yielded by older standard experimental protocols. An application to the experimental observation of the temperature dependence of the tunneling current is proposed. Conclusions about the benefits of this kind of electrical measurements are then drawn. (C) 2014 Elsevier Ltd. All rights reserved.

■ Abstract Among the heavy metal-binding ligands in plant cells the phytochelatins (PCs) and metallothioneins (MTs) are the best characterized. PCs and MTs are different classes of cysteine-rich, heavy metal-binding protein molecules. PCs are enzymatically synthesized peptides, whereas MTs are gene-encoded polypeptides. Recently, genes encoding the enzyme PC synthase have been identified in plants and other species while the completion of the Arabidopsis genome sequence has allowed the identification of the entire suite of MT genes in a higher plant. Recent advances in understanding the regulation of PC biosynthesis and MT gene expression and the possible roles of PCs and MTs in heavy metal detoxification and homeostasis are reviewed.

On CMOS technology, some process steps can create a parasitic phenomenon named “hump effect.” This parasitic effect can have a strong impact on gate voltage matching of differential pairs and, as a consequence, on analog circuit performances. In this context, several solutions to limit or remove this hump effect are proposed and described. Silicon data obtained at package and wafer levels for different temperatures are analyzed.