We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random timing mismatches among current sources. To decode the DAC input codewords into corresponding DAC switches, we present three algorithms with varying computational complexities. We perform high-level Matlab simulations to illustrate the dynamic performance improvement over the segmented structure.
A mixed-signal hardware accelerator for solving a modern Hopfield network (MHN) is presented. Unlike classical Hopfield networks (CHNs), MHNs offer significantly higher storage capacities while requiring fewer updates to reach a solution. The proposed accelerator integrates digital storage and binary computation with analog current-mode processing to implement the exponential interaction functions essential for the strong nonlinearity characteristic of MHNs. Designed in TSMC 65nm CMOS technology, the network consists of eight 8-bit binary neurons. Circuit simulations across 256 input combinations demonstrate that, when prompted with an input, the eight-neuron network converges to one of eight stored patterns within two asynchronous update cycles, taking 1.08 ms. Of all inputs, 91% are transformed into either the closest or second-closest stored pattern, as measured by Hamming distance. Supplied by a single 1V supply, the accelerator consumes $63.3 \mu \mathrm{W}$, which makes it the most power-efficient solution among CHN or CHN-based associative memory hardware accelerators compared. Achieving eight pattern storage using only eight neurons, the proposed accelerator demonstrates the significant efficiency of MHNs in terms of patterns stored per neuron in an energy-efficient manner.
This paper discusses alternative implementations of radio-frequency (RF) analog-to-digital converters (ADCs) by using bandpass delta-sigma modulators $(\text{BP}-\Delta\Sigma \text{Ms})$. Main architectural strategies, including loop-filter order, quantizer resolution, notch-frequency position, undersampling, and feedback digital-to-analog converter (DAC), are overviewed while considering their practical limitations in terms of system complexity, stability, dynamics, and power consumption. Additionally, the combination of tunable notch-frequency and bandpass finite impulse response (FIR) filtered DAC is discussed as an efficient approach, offering reduced sensitivity to nonlinearities and clock jitter compared to the prior art1.
This paper explores a trajectory-based local navigator for mobile robots in which system identification is used to identify a kinodynamic model that generates trajectories capturing vehicle drivability constraints. A physics-based differential-drive model produces the ground-truth dataset which in combination with velocity command sequences inform an Auto-Regressive eXogenous input (ARX) system framework. Experimental evaluations are conducted across diverse driving scenarios and vehicle loading conditions, incorporating both training and validation datasets. The identified models demonstrate strong predictive capability, with the resulting trajectories closely matching groundtruth paths and validating the effectiveness of the proposed approach.
Dual-output look-up tables (LUTs) are supported by modern commercial Field-Programmable Gate Array (FPGA) architectures. Existing technology mapping usually generates dual-output LUTs by merging single-output LUTs. However, these mapping solutions often fail to fully leverage the dual-output capability. This paper introduces a novel FPGA mapping scheme for dual-output look-up tables (LUT), designed to improve synthesis performance significantly. By introducing new metrics functions, kl-cut generation method, and methods to add secondary LUT outputs, the proposed approach enables thorough exploration of the design space. Synthesis results show that the proposed method achieves $\mathbf{3 0. 2 \%}$ and $\mathbf{3 2. 0 \%}$ improvement in LUT usage and depth when mapping dual-output LUTs, outperforming leading-edge mapping tools.
