This paper presents a MATLAB-assisted EKV–gm/ID methodology for the systematic synthesis of fully differential two-stage Miller-compensated CMOS OTAs. A sensitivity-based analysis maps the required closed-loop gain, bandwidth, and noise into OTA-level targets. An EKV-inspired analytical model, independently calibrated for nMOS and pMOS devices, provides continuous ID/W, gm/W and gm/ID characteristics with errors below 5% in the design region. Noise-driven sizing explicitly accounts for the different carrier mobilities of the pMOS differential pair and nMOS active load. Transistor parasitic capacitances are estimated from bias-dependent Cgg–VGS characteristics, thereby capturing the reduced gate capacitance of devices operating in moderate or weak inversion. The framework automatically generates transistor dimensions, bias conditions, and Miller-compensation components. These parameters are transferred directly from MATLAB to CADENCE without simulator-assisted resizing or optimization, except for width quantization into 5 μm/300 nm fingers. In 0.18 μm CMOS implementation, MATLAB and nominal CADENCE simulations predict, respectively, 61.80 and 59.27 dB DC gain, 430.78 and 431.52 MHz unity-gain bandwidth, 69.24° and 68.81° phase margin, 5.0 and 5.3 nV/√Hz input-referred noise at 100 MHz, and 1.426 and 1.314 mW core power. Robustness is assessed over 45 process-voltage-temperature corners, where the nominal solution remains close to the center of the evaluated performance distributions. The results confirm accurate nominal prediction and stable transistor-level behavior across PVT conditions and demonstrate that the proposed methodology accurately designs the OTA operating point, small-signal dynamics, and noise behavior, enabling transistor-level sizing directly from system-level specifications without iterative simulator-assisted optimization.
Processing-in-memory (PIM) architectures have emerged as promising alternatives to conventional von Neumann architectures for accelerating memory-bound applications, such as Graph Neural Networks (GNNs), by reducing data movement between memory and processing units, thereby improving energy efficiency and reducing computational latency. Feature aggregation is a fundamental operation in GNNs; however, the sparsity of graph data leads to poor spatial and temporal locality. This results in dynamic and irregular memory access patterns, ultimately limiting performance and increasing latency. To address this issue, we propose LUPIN, a look-up table (LUT)-based PIM architecture to accelerate GNNs. In this design, logic-based processing is replaced with precalculated results stored in LUTs to perform the required computations within the DRAM memory platform. The proposed LUPIN architecture achieves enhanced performance and markedly improved energy efficiency compared to conventional bitwise-parallel PIM designs. Moreover, it avoids the fabrication challenges associated with integrating logic circuits into memory. It leverages the extensive internal parallelism of DRAM to accelerate the execution of GNN models while maintaining high energy efficiency. Our results demonstrate that LUPIN achieves geometric-mean energy improvements of 32× and 51× on GCN and GIN, respectively, over the CPU and 15× and 19.5×, respectively, over the GPU. Moreover, LUPIN reduces latency by 35.8× and 25.7× on GCN and GIN, respectively, compared with the CPU and 29.6× and 20.5×, respectively, compared with the GPU. The proposed LUPIN architecture achieves nearly 10× higher energy efficiency and 5× speedup compared with the state-of-the-art PIM architectures.
Polytetrafluoroethylene (PTFE) is an important dielectric and structural substrate for high-frequency, flexible, low-background, and other electronic systems because of its low dielectric loss, high electrical resistivity, low moisture absorption, chemical inertness, and thermal stability. However, its fluorine-rich surface, low surface energy, and weak boundary layer hinder metal nucleation and interfacial bonding, frequently leading to discontinuous film growth, high interfacial resistance, and premature delamination. This focused review summarizes recent progress in low-temperature plasma-assisted metallization of PTFE, with particular emphasis on the relationships among plasma activation, interface formation, electrical functionality, reliability, and manufacturability. The effects of plasma-induced physical etching, defluorination, radical generation, polar functionalization, weak-boundary-layer removal, and hydrophobic recovery are first discussed. Representative metallization routes are then reviewed, including direct physical vapor deposition, plasma-assisted electroless plating, plasma-induced grafting, metallic interlayers, ion implantation, and hybrid plasma-deposition processes. Particular attention is given to interface-strengthening mechanisms involving chemical bonding, mechanical interlocking, diffusion control, carbon-rich or graded transition regions, and interdiffusion. The key trade-offs among adhesion strength, conductor resistance, dielectric integrity, surface-modification stability, and mechanical or environmental reliability are further analyzed for electronic-substrate applications. Although metallic interlayers, ion implantation, and hybrid processes can provide more stable interfaces than plasma activation alone, challenges remain in controlling plasma-induced damage, surface aging, interfacial carbonization, and process reproducibility. Recent 2024–2026 studies further show that these interface technologies can translate into low-loss Cu/PTFE laminates, flexible circuits, integrated vacuum metallization stacks, and selectively patterned conductors. The relevance to low-power systems is therefore treated as one application context at the substrate/interconnect level rather than as evidence that PTFE metallization directly reduces circuit switching power.
Edge Artificial Intelligence (Edge AI) is used in wildlife monitoring to reduce communication demand, support decision-making, and enable energy-aware operation, yet embedded inference alone does not establish whether a system can sustain useful service after installation. This scoping review searched four bibliographic databases through 5 August 2026 and complemented these searches with studies identified from prior work on the topic, identifying 41 eligible English-language papers published from 2021 onward on camera-primary intelligent wildlife systems. The review aimed to assess operational maturity, field-validated operational role, energy evidence, and operational continuity. Full texts were charted and analyzed across sensing, decision-making, communication, response, energy, and continuity. Post-installation evidence exposed triggering, environmental, connectivity, maintenance, and energy-supply constraints not established through non-field evaluation. Field-validated alert delivery did not extend to quantitative validation linking human action to mitigation outcomes, while field activation of physical intervention alone did not establish behavioral or management effectiveness. Energy evidence was even more limited, with limited direct operational electrical measurement, rare main-state characterization, and no complete lifetime energy budget evidence. By separating architectural capability from the evidence supporting its operational realization, the review provides a systems-level basis for interpreting how far reported functions are actually validated. Across the corpus, optimization often shifts constraints among computation, triggering, communication, energy supply, and availability rather than eliminating them. Wildlife Edge AI should therefore be evaluated as a complete field system under application-relevant conditions.
Polynomial fitting is widely used for analog circuit calibration but is sensitive to polynomial order and can become numerically unstable at high orders. This paper presents a systematic comparison between a lightweight Gradient Boosting Decision Tree (GBDT) approach and classical interpolation methods for analog circuit calibration, using two case studies: a 0–100 dB variable-gain amplifier (VGA) and a low-dropout regulator (LDO) under three operating conditions. Unlike prior work that reports only fitting accuracy, we evaluate predictive generalization using leave-one-out and repeated random hold-out validation, with all hyperparameters selected on the training set only. The experimental results show that method selection depends critically on data characteristics and that the advantage of GBDT is far less general than commonly assumed for the smooth one-dimensional calibration datasets investigated in this work. On smooth, one-dimensional calibration data—including the VGA and all three LDO sweeps—polynomial fitting, piecewise-linear interpolation, and cubic splines consistently achieve lower held-out error than GBDT. For example, on the VGA dataset, the held-out MAE of GBDT is 1.02 dB, whereas polynomial fitting achieves 0.0072 dB and piecewise-linear interpolation 0.0055 dB. GBDT does not provide a systematic advantage under sparse sampling in the one-dimensional cases studied here; its apparent zero-error behavior in earlier fitting-only evaluations is shown to reflect training-set memorization rather than predictive accuracy. The trained GBDT models remain lightweight (97–250 KB) with sub-millisecond inference time, but on the smooth, low-dimensional data considered in this work, classical interpolation methods are the preferred choice. This work provides practical, data-driven guidance for method selection in analog circuit calibration and clarifies the conditions under which tree-based models are and are not appropriate.
