A System-on-chip (SoC) accommodates different security-sensitive modules and information, collectively known as assets. Protecting the assets from a malicious entity is the key objective of the security architecture of the SoC. On the other hand, optical debugging and diagnosis based physical inspection methods are widely used for defects and failures localization in silicon implementation. Transparency of silicon to near-infrared (NIR) light is used for optical debugging purposes, e.g., photon emission analysis, laser-voltage probing/imaging, laser stimulation. The mentioned above semi-/non-invasive optical approaches allow run-time monitoring of the transistor through a silicon substrate, i.e., chip backside. Besides, to facilitate the failure analysis, no protection scheme is implemented at the SoC backside. Therefore, an attacker can effortlessly track and extract the chip assets by optically attacking the security-sensitive modules. Thus, the silicon substrate appears as the new "back-door" for SoC security. Though different countermeasures have been proposed, none proved to be impeccable against different classes of optical attacks. Therefore, to identify the attack surface for optical attacks, we surveyed the security threat imposed by various optical attacks. Based on the capability and chip design asset availability, we have also classified the potential adversaries to exploit the semi-invasive optical techniques. Finally, we turned our focus about the threat of optical attacks in the existing and emerging smaller technology nodes and concluded with suggestions for future research direction.
With the ever-increasing demand for portable electronic devices to provide longer battery life, extremely low power consumption becomes an SoC design imperative. Aggressive SoC and system-level power management methods (PMM) are key to this drive towards low power consumption and extended battery life. These methods pose many challenges to the validation of the low-power states, SoC and system-level debug, and overall product time to market (TTM). This paper discusses techniques developed to address these SoC validation and debug challenges efficiently.
Modern SoCs are developed by integrating several hundreds of IPs like hardware accelerators, I/O interfaces, memories, controllers, third party IPs, etc. It mostly uses several interconnects or cache coherent network for integration. Such complicated SoCs are prone to design errors that may affect, not only functionality but also performance. Performance bugs are much more difficult to detect in comparison to functional bugs. Even bug free performance will vary for a given application for a given SoC micro architecture and RTL design parameters. In majority of cases, performance bug detection and localization have been conducted manually and these are very challenging tasks. To localize such performance bugs in micro-architecture of various design components or interconnects using emulator/FPGA based environment is very challenging task. In this paper, we are discussing three approaches to deal with such problems. One approach deals with detection of critical data paths of the design by drawing directed graph of data paths. Later, dynamic performance simulations are run on those paths of the design by stressing all relevant design units. The second approach is about localization of performance bug. Third approach is to extract the RTL design parameters of the various components and analyze these parameters with various stakeholders before declaring the logic freeze of the device. On applying these, we found some critical performance bugs in design which were not found with conventional techniques. The proposed methodologies reduced overall performance verification time and improved quality of design.
Reconfigurable logic enables architectural updates for embedded devices by providing the ability to reprogram partial or entire device. However, this flexibility can be leveraged by the adversary to compromise the device boot process by modifying the bitstream or the boot process with physical or remote access of device placed in a remote field. We propose a novel multilayer secure boot mechanism for SoCs with a two-stage secure boot process. First stage uses device bound unique response as a key to decrypt application logic. The security function is extended at runtime by integrating intermittent architecture and application locking mechanism to reveal correct functionality.
As projects approach their deadlines, multiple teams - design and verification - are running several simulations and regressions. Many times, the test logs and waveforms across several TestBenches lie around way past their usefulness. This causes project delays as space reduces to such an extent that no simulations or work can proceed or at a glacial pace. We've experienced the same across several projects and have come to a better way to manage and administrate these disks by using the ageing mechanism effectively by giving users and disk administrators relevant information and controls.
