Network-on-Chip (NoC) architectures are widely used in many-core systems due to their scalability. Threedimensional NoCs further improve performance by stacking multiple layers using Through-Silicon Vias (TSVs), at the cost of increased routing complexity. Deterministic routing algorithms often suffer from congestion under non-uniform traffic, motivating adaptive solutions. In this paper, we present a learningbased adaptive routing approach for 3D NoCs that stabilizes Q-learning-based routing decisions using a beta-regulated probabilistic selection mechanism. Direction-based learning is employed to reduce learning complexity. Experimental results show improvements in latency and throughput compared to deterministic and conventional adaptive routing schemes.
This work investigates proposed maximum-powerpoint tracking (MPPT) approaches for a fully integrated hybrid voltage converter (H-VC) intended for alternative energy sources in low-power Internet of Things (IoT) systems, where passive components and power supply rail stability impose severe constraints. A monolithic Hybrid-Dual-Path (HDPC) voltage converter with an on-chip $L_{\text{DC}}=15.07 n H$ inductor and strongly limited total capacitance ($C_{\text{IN}}=C_{\text{OUT}} \approx 2.5 n F$) is considered, with 1.5 V output voltage regulation provided by a continuously operating shunt-type regulator. The two MPPT concepts are analyzed: (i) iMPPT based on the fractional open-circuit-voltage (FOCV) principle, which is energy-efficient but requires periodic $V_{\text{IN,OC}}$ sampling via short-time disconnection of alternative energy sources (AES), and (ii) oMPPT, which maximizes extracted load power by optimizing the combined product $\eta_{\text{MPPT}}.\eta_{\text{VC}}$ and provides instantaneous power observability in a form of digital code. The feasibility and performance are evaluated in Cadence using a TSMC 65 nm CMOS technology and a realistic PV model (KXOB25-14X1F), across irradiance levels of 5-500 W/m2 corresponding to PIN,MPP from $114 \mu W$ to 14.8 mW. Simulation results show that both approaches regulate operation over a wide switching-frequency span of roughly 0.9-62 MHz via FrequencyShift Modulation Control (FSM-C). Overall, iMPPT is favored when minimal control overhead is paramount, whereas oMPPT offers superior scalability and algorithmic flexibility for broader AES applicability at the cost of up to 5.5 times higher power consumption.
Post-Quantum Cryptography (PQC) schemes, such as Learning with Errors (LWE), rely on adding Gaussian noise to arithmetic operations to achieve security against quantum adversaries. Efficient generation of this noise is critical for hardware implementations, particularly in resource-constrained environments like IoT devices. Traditional approaches employ Gaussian samplers to produce discrete Gaussian noise, but these methods introduce significant area overhead and latency, limiting their practical applicability. In this work, we propose a novel hardware architecture that generates Gaussian-like noise using controlled XOR-based bit-flip operations integrated directly into arithmetic circuits. Our approach achieves up to a $3 \times$ reduction in area compared to conventional hardware Gaussian samplers, while introducing negligible delay. The resulting architectures provide an efficient and lightweight solution for noise injection, making them highly suitable for deployment in constrained hardware platforms.
This work presents a low-power analog artificial neural network for Star Evolutionary Phase Classification, implemented in a mixed-mode integrated architecture. The design employs a Swish activation function in the input layer and a voltage-to-current Bump-AntiBump circuit in the hidden layer for energy-efficient computation. A current-mode feature correlator based on an Euclidean Distance Circuit performs similarity assessment between feature vectors, while a Loser-Takes-All circuit ensures reliable classification. All analog blocks operate in the sub-threshold region, enabling sub-microwatt power consumption with a 0.6 V supply. Implemented in TSMC 65 nm CMOS within the Cadence IC Suite, the proposed ANN achieves a median classification accuracy of 94.0 % and an average power consumption of 967 nW. Comprehensive corner and Monte Carlo simulations confirm robustness against mismatch and process variations. Compared to software implementations and prior analog classifiers, the proposed design demonstrates superior energy efficiency and high accuracy, making it well suited for wake-up analog front-end applications.
Deep neural networks (DNNs) have high computational and memory demands because they rely on multiplyaccumulate (MAC) operations and the amount of data that needs to be moved from the main memory to the compute unit. Since 2016, Systolic Arrays have emerged as a popular architecture for accelerating DNNs inference, although their performance is affected by multiple parameters, including the amount of used Processing Elements (PEs) and the dataflow. In this study, we perform a systematic evaluation of Systolic Array-based DNN accelerators using the ScaleSIM simulation framework to analyze different array sizes and dataflow configurations across different DNN models, measuring the effects of memory transfers, and execution latency across all DNN workloads, founding that dataflow option for routing data through an array is dependent on the specific workload; thereby, using moderate array sizes can achieve better performance than larger arrays, offering useful insights for Systolic Array-based DNN accelerators design.
