As an approximate membership query filter, the Xor Filter (XF) provides benefits including a smaller memory footprint and faster lookups compared to Bloom filters (BFs) and Cuckoo filters (CFs); these characteristics are highly desirable in many applications, hence their widespread use in nanoscale storage systems and nanosensors. However, a concern remains on the dependability of XFs in critical applications; soft errors, such as a Single Event Transient (SET) and a Single Event Upset (SEU), can cause errors in the hardware or stored data, leading to false positives or false negatives in the XF queries. False negatives are critical as by construction they are not present in fault-free filters. Unlike prior work that mainly characterized the vulnerability of XFs, this paper develops lightweight fault-tolerant designs that exploit the XF's inherent characteristics to mitigate these faults. The evaluation results demonstrate that the proposed schemes can fully avoid false negatives at a very small overhead. An FPGA implementation further quantifies the hardware, power, and latency overheads of the proposed protection schemes, showing the efficiency of the schemes.
In this article, we present a physics-based gate current model for p-GaN/AlGaN/GaN high electron mobility transistors (HEMTs), valid across a wide bias, and broad temperature range. Unlike the existing gate current models valid upto nominal temperatures only, this work for the first time provides a modeling framework for gate leakage of p-GaN HEMTs valid down to cryogenic temperatures of 10 K. The model is based on various leakage mechanisms, with each mechanism determining the conduction across different gate bias and temperature ranges. By leveraging the device electrostatics and incorporating the characteristic effects associated with cryogenic temperatures such as bandgap widening and incomplete ionization, a unified gate current model for p-GaN HEMTs is established. The proposed model is benchmarked against both in-house experimental data and measurement results available in the literature to ascertain its validity across a wide range of bias and temperature. This work aims to serve as a fast and efficient tool for the reliable circuit design using p-GaN gate HEMTs for advanced cryogenic applications.
Mode-division multiplexing switches with larger N × N scales remain largely unexplored due to high optical losses, limiting their scalability. To address this, we present a highly scalable dual-mode ($\text{TE}_{0}/\text{TE}_{1}$) $N\times N$ ($N=2,4,8$) photonic switch. The design employs a non-blocking rectangular Clements topology, enabling arbitrary unitary matrix decomposition for both modes and increasing routing degrees of freedom. The proposed structure utilizes an optimized ultra-low-loss dual-mode directional coupler at $\text{1550}~\text{nm}$. The $8\times 8$ switch, it achieves low insertion losses of $\text{0.089}~\text{dB}$ ($\text{TE}_{0}$) and $\text{0.120}~\text{dB}$ ($\text{TE}_{1}$), with crosstalk of $-43.76~\text{dB}$ and $-41.29~\text{dB}$, respectively. Occupying a footprint of $\sim 8604~\mu \mathrm{m}\times 150~\mu \mathrm{m}$, the switch exhibits thermal response times of $16.76~\mu \mathrm{s}$ (rise) and $22.60~\mu \mathrm{s}$ (fall). Additionally, an added tuning layer enables post-fabrication phase error correction to enhance scalability and robustness. Successful $\text{25}~\text{Gbps}$ OOK data transmission analysis shows its strong potential for scalable, programmable multimode optical interconnects for telecommunication and computing applications.
