In the present study, I-V curves and EFM-Phase measurement for surface polishing treatments are used in order to obtain electrical properties like breakdown voltages, leakage currents and Schottky Diode Barrier Height (SBH) calculated by Thermionic Emission model (TE) and parabolic model of EFM-Phase. The results showed that a polishing treatment with 0.03 μm grain size alumina powder solution induces a higher SBH, lower leakage current and higher breakdown voltage compared to that with 1 μm alumina solution.
Periodic quantum dot solids are new materials in which quantum dots are periodically distributed in space. The properties of these materials are explored to find applications in new photovoltaic devices. In order to shed light on these future applications, investigating carrier transport and light absorption are of paramount importance. The first step to investigate these systems is to compute their electronic structures. In this work we present the electronic structure of one- (1D), two- (2D) and three-dimensional (3D) quantum dot solids made of 12 Å radius InAs quantum dots. Two different stoichiometries are studied. In the first case (system A) the quantum dot has an In atom in its center and the interdot contact surfaces along the (111) directions in the arrays are mainly arsenic atoms. In the second case (system B) the atomic positions are inverted, and therefore the contact surfaces between neighbours are mainly indium atoms. The influence of dimensionality and stoichiometry in these quantum dot solids are discussed.
Nowadays, bio-inspiration is driving novel sensors designs, beyond vision sensors. By taking advantage of their compatibility with standard CMOS technologies, the integration of giant magneto-resistance (GMR) based magnetic sensors within such event-driven approaches is proposed. With this aim, several topologies of such GMR sensors have been designed, fabricated and characterized. In addition, integrated circuit interfaces of a standard CMOS technology are also proposed. Their suitability for this approach is then demonstrated by means of Cadence IC simulations.
In this work we study the self-heating effect (SHE) in nanoscale Silicon on Insulator Junctionless (SOI JL) FinFET transistor with fin cross section in rectangular, trapeze and triangle form. The lattice temperature dependence on the channel length as well as on buried oxide thickness is considered. It is shown that for considered transistor structure the lattice temperature in the middle of the channel is lower than at lateral sides, near source and drain. Also, we have found at the same conditions the lattice temperature depends on shape of channel cross section too.
Virtual Ge substrates fabricated by direct deposition of Ge on Si have become a pathway with high potential to attain high-efficiency III-V multijunction solar cells on Si. We study the development of III-V triple junction solar cells using two types of Ge|Si virtual substrates. The first uses a thick (2–5 μm) Ge layer grown by CVD, which acts as the bottom Ge subcell. The second, grown by low-temperature RT-PECVD, has a thickness of a few tens of nanometres, with the Si substrate acting as Si bottom cell. We discuss the challenges related to each design (formation of cracks, parasitic absorption in the Ge layer, dislocations, …), present the theoretical design and show the experimental results obtained. Finally, an advanced approach using embedded porous Si layers as buffer layers for crack mitigation is also presented.
