The discovery of ferroelectricity in hafnia-based thin films has paved the way for their integration into non-volatile memory technologies, offering compatibility with CMOS processes and the potential for aggressive scaling. One significant aspect impacting the reliability and performance of ferroelectric Hf0.5Zr0.5O2 (HZO) capacitors is the oxygen vacancy (VO) concentration, which influences endurance, retention, and polarization stability. This study investigates the VO concentration profile for the woken-up state (10(4) cycles) in HZO-based ferroelectric capacitors (FeCAPs) in different polarization states (P. and P.). The VO distribution is quantified using Hard X-ray photoemission spectroscopy (HAXPES), using incident photon energies from 3 to 9 keV to calculate the VO concentration profile across the HZO layer non-destructively. Results indicate that VO accumulates near the top TiN/HZO interface for the P. state, while they drift toward the bottom HZO/TiN interface for the P. state under the effect of the internal polarization field. This polarization-dependent VO distribution correlates with voltage and field offsets observed in electrical measurements, providing insights into defect mobility that can inform FeRAM device optimization. Our results show that the polarization behavior, i.e. the alignment and stability of electric dipoles within the HZO layer, strongly correlates with the distribution of VO, which plays a crucial role in enhancing the reliability and performance of ferroelectric memory devices. These findings enhance our understanding of the coupling between defect chemistry and ferroelectric properties in HZO, supporting the engineering of high-performance, CMOS-compatible ferroelectric memory technologies.
In this study, various charge trapping mechanisms and their effects on the endurance of n- and p-type HfO 2 -based FeFETs, integrated within GlobalFoundries 28 nm bulk high-k metal gate (HKMG) technology are examined. The device's endurance is impaired due to pronounced interface degradation and charge injection into the Metal-Ferroelectric-Insulator-Semiconductor (MFIS) gate stack caused by the high interfacial field stress. By analyzing threshold voltage shifts under both bipolar and unipolar cycling, as well as bipolar endurance cycling for “non-ferroelectric” samples with diminishing remanent polarization levels, the study reveals the critical role of polarization switching in endurance degradation. The findings highlight the deterioration of the gate stack and specifically of the interface of FeFETs upon bipolar cycling which strongly affects the electrical characteristics and causes increased electron trapping in n-type-FeFETs and hole trapping in p-type FeFETs. This effect is particularly pronounced for each device's low threshold-voltage (LVT) state and is intensified by polarization switching. The study's results contribute to a deeper understanding of the charge trapping phenomena in HfO 2 -based FeFETs and their impact on device performance and reliability.
Training neural networks for large-scale applications such as pattern extraction and speech processing are time and resource-intensive. The utilization of crossbar architectures designed with non-volatile memories (NVMs), such as Resistive RAMs (RRAMs), facilitates in-memory computing and can accelerate the training process, including forward and backward passes. To accelerate the weight update process, Resistive Processing Units (RPUs) are incorporated at the crosspoint in arrays. However, RRAMs can only represent a limited number of conductance levels, which affects the accuracy of weight gradient calculation, thus affecting the accuracy of the overall network. In the literature, a requirement of 1000 conductance levels in memristors for efficient training, especially weight update operation using RPU, is shown. In prior works, to achieve more conductance levels, multiple memristors are used for a single-bit cell. However, for a linear increase in levels, a linear increase in hardware is needed to be employed. In this work, we propose an area-efficient multi-RRAM bit cell design to attain the required number (1000) of conductance levels and model the bit cell to quantitatively show > 86% accuracy using a hardware-efficient scheme. The RRAMs are connected in a weighted conductance manner, increasing conductance exponentially for a linear increase in hardware. We show a similar to 33x reduction in RRAM devices and similar to 5.6x reduction in transistor count per bit cell with our proposed design to achieve 1000 levels.
Nonvolatile memories (NVMs) have emerged as promising candidates for efficient analog compute-in-memory (CIM). However, high power consumption and large variations in NVMs are key factors hindering the performance of analog computing. In this work, we demonstrated an 8Kb 1T-1R CIM macro-array utilizing spin-orbit torque (SOT) magnetic random-access memory (MRAM). The SOT-MRAM features high cell resistance at parallel magnetization configuration (RP) of 2MO and low resistance standard variation-to-average ratio of 4.2% The CIM array achieves 10ns write speed and no endurance failures up to 1010 write cycles. Moreover, the linear analog multiply-accumulate (MAC) output maintains a sufficiently high accuracy, making it well-suited for binary neural network (BNN) applications in edge devices.
The development of scalable and CMOS-compatible cryogenic quantum processors necessitates embedded non-volatile random-access memory to support computation while controlling heat generation under cryogenic conditions. However, conventional memory technologies based on magnetoresistive and resistive effects encounter significant self-heating issues. Consequently, hafnium oxide-based ferroelectric field-effect transistors emerge as a promising alternative. In this study, we first evaluated their endurance across various temperatures, including cryogenic temperatures down to 2 K. We then characterized their temperature-dependent data retention behaviour at each temperature, observing and discussing a notably long electron detrapping time at 2K. Additionally, we analyzed the flicker noise of the transistors in two ferroelectric polarization states.
