Efficient performance prediction at the source code level is essential in reducing the turnaround time of software development. In this paper, we introduce a new prediction model, which combines several machine learning algorithms, such as KNN, clustering, similarity, sample and attribute weighting with multiple linear regression techniques, to predict the execution time of Digital Signal Processing (DSP) software at the source code level. Prediction at source code level tends to both under-predict the performance for certain testing samples and over-predict for some other samples. Therefore, we propose a new algorithm called MAX/MIN algorithm to select the best-predicted execution time. To validate the new model, we measure experimentally the execution time of a set of functions selected from PHY DSP Benchmark and run them on TIC64 DSP processor. It is observed that the average absolute relative prediction error is less than 10% between the computed performance from the new model and the actual measured execution time.

Machine learning (ML) is becoming a powerful tool for a variety of applications where artificial intelligence solutions are required. A ML benchmark is a standard suite to measure, evaluate and compare the performance and efficiency of ML systems. This study analyzes the benchmark results from two famous benchmarks MLMark and MLPerf to provide a basis of comparison between both benchmarks as well as to provide recommendations on computer architectures to utilize for ML inferencing. Lastly, special emphasis is placed on the performance of edge AI devices.

Efficient performance prediction at source code level is essential in reducing the turnaround time of software development, particularly when the source code is subject to changes due to modification of problem specification. In this paper, we investigate and compare five performance prediction models from practical standpoint to determine the usefulness of these models. To verify the effectiveness of these models, we select a set of functions from PHY DSP Benchmark and TIC64 DSP processor for experiment. Comparing the predicted performance to the actual measured execution time, we observed that the relative prediction error generated from two of the five models are low and can thus be used for practical purposes.

Performance prediction is critical in embedded system design for reducing the turnaround time of software. Using simulation to measure the performance of the whole source code is often too slow, particularly after the modification of the source code due to changes in problem specification. In this paper we present a comprehensive method that combines analytical modeling and statistical approach to predicting the performance of application software at source code level. We take samples from EEMBC and SMV benchmarks and gather the static attributes from the source code of those samples as our learning set. To determine the effectiveness of our new approach, we select several functions from PHY Benchmark as our testing set. We then apply multiple linear regression technique enhanced with the inclusion of new approaches by using the popular statistical tool SPSS23 to predict the performance of these functions. Comparing our predicted results with the actual measured values, the outcome is promising as the average relative error is within 20%.

Instruction level loop optimization has been widely used in modern compilers. Decompilation—the reverse of compilation—has also generated much interest for its applications in porting legacy software written in assembly language to new architectures, re-optimizing assembly code, and more recently, in detecting and analyzing malware. However, little work has been reported on loop decompilation at instruction level. In this paper, we report our work on loop de-optimization at instruction level. We demonstrate our approach with a practical working example and carried out experiments on TIC6x, a digital signal processor with a compiler supporting instruction level parallelism. The algorithms developed in this paper should help interested readers gain insight especially in the difficult tasks of loop rerolling and software de-pipelining, the necessary steps to decompile loops at instruction level.

Instruction level loop optimization has been widely used in modern compilers. Decompilation-the reverse of compilation-has also generated much interest for its applications in porting legacy software written in assembly language to new architectures, re-optimizing assembly code, and more recently, in detecting and analyzing malware. However, little work has been reported on loop decompilation at instruction level. In this paper, we report our work on loop de-optimization at instruction level. We demonstrate our approach with a practical working example and carried out experiments on TIC6x, a digital signal processor with a compiler supporting instruction level parallelism. The algorithms developed in this paper should help interested readers gain insight especially in the difficult tasks of loop rerolling and software de-pipelining, the necessary steps to decompile loops at instruction level.

Abstract— Large amount of software for embedded digital signal processing systems is written in assembly language. Software pipelining of loops is necessary to exploit the full potential of Very Long Instruction Word (VLIW) processors. For both understanding software pipelined loops and reverse compiling them to high level language code the software pipelined loops must be de-pipelined back to the original loops. In this paper we present technique for software de-pipelining of nested loops, demonstrate it with an example and evaluate the benefits of some software pipelined nested loops.

The digital signal processor (DSP) industry has been growing steadily over the past few years due to strong demands for digital signal processors in a variety of applications. Among these applications, wireless communication accounts for more than two-thirds of the DSP market today. The Selectable Mode Vocoder (SMV) is a third generation (3G) speech coding technology that provides significant capacity and quality improvements over the second generation. SMV is very complicated and its implementation requires much CPU time and memory space. It has therefore been a challenge to implement SMV efficiently on a DSP chip. We present in this paper a thorough analysis of loop behavior in SMV because DSP processors spend most of their time in loops. We also evaluate the impact of the behavior of the loops on instruction level parallelism. Our motivations are: 1. to identify typical and frequently executed functions as potential new DSP benchmarks, and 2. to obtain information that might lead to the improvement on the designs of DSP optimizing compilers and architecture of DSP processors. We first developed our own profiling tool, which is capable of operating at both function and loop levels. We also used static analysis in combination with dynamic measurement techniques to characterize the behavior of the loops. Based on the data collected from more than 250 loops selected from the frequently executed functions of SMV, we present 1. basic data on the SMV program such as the number of weighted DSP operations, 2. the behavior of various loops such as the maximum and minimum numbers of loop iterations; loop types; number of exits from and number of conditional branches in loops; characteristics of the nested loops; and the distribution of various kinds of DSP operations in loops. All data are analyzed and discussed in the context of architecture of DSP processors and instruction level optimization approaches to DSP compilers.

Digital signal processing (DSP) industry has been growing rapidly over the past few years; it remains the technology driver for the recovering semiconductor industry. Performance evaluation is essential for the users and manufacturers of DSP processors. Since DSP application programs become larger and more complicated, people need new benchmarks for performance evaluation of different DSP processors. We build a new DSP benchmark based on Selectable Mode Vocoder (SMV), a speech-coding program from the 3G wireless applications. Our new DSP benchmark, called SMV benchmark, consists of eight kernel functions. In this paper, we introduce the criteria of selecting kernels and our methodology to build SMV benchmark. We also discuss the characteristics and static analysis of the kernels.

Software pipelining is a loop optimization technique that is widely implemented in modern optimizing compilers. In order to fully utilize the instruction level parallelism of the recent VLIW DSP processors, DSP programs have to be optimized by software pipelining. However, because of the transformation of the original sequential code, a software-pipelined loop is often difficult to understand, test, and debug. It is also very difficult to reuse and port a software-pipelined loop to other processors, especially when the original sequential code is unavailable. We propose a de-pipelining algorithm which converts the optimized assembly code of a software-pipelined loop back to a semantically equivalent sequential counterpart. Preliminary experiments on 20 programs verify the validity of the proposed de-pipelining algorithm.

Software pipelining is an effective technique to reduce cycle count by exploiting instruction level parallelism in loops. It has been implemented in most VLIW DSP compilers. However, software pipelining expands the code size due to the introduction of prelude and postlude. To address this problem, many VLIW DSP compilers include certain code size reduction features. During compilation, a user is given limited options of exercising these code reduction features. As a result, the tradeoff options between cycle count and code size are also limited. Yet today's software development often requires an optimum balance between code size and cycle count, which in turn requires a much wider tradeoff space. This paper presents a new heuristic code-size-constraint loop optimization approach to extend the tradeoff space. Preliminary experimental results indicate that the new approach can significantly widen the tradeoff space, thus providing DSP users with more flexibility to meet their various design criteria.

Software pipelining is a loop optimization technique that has been widely implemented in modem optimizing compilers. In order to utilize fully the instruction level parallelism of the recent VLIW DSP processors, DSP programs have to be optimized by software pipelining. However, because of the transformation of the original sequential code, a software-pipelined loop is often difficult to understand, test, and debug. It is also very difficult to reuse and port a software-pipelined loop to other processors, especially when the original sequential code is unavailable. We propose a de-pipelining technique, which converts the optimized assembly code of a software-pipelined loop back to a semantically equivalent sequential counterpart. Preliminary experiments on 20 assembly programs verifies the validity of the proposed de-pipelining algorithm.

In order to fully utilize the instruction level parallelism of VLIW DSP processors, DSP programs have to be optimized by software pipelining. Software pipelining has been studied for many years and widely implemented in optimizing compilers. However, due to the rearrangement of the original instructions, it is often very difficult to re-use or port the code of a software-pipelined loop to other processors. In this paper we present a practical approach to solve this problem. Our approach involves the following steps: (1) Using a newly developed software de-pipelining algorithm to convert the assembly code of a software-pipelined loop to a semantically equivalent sequential loop; (2) Using our pattern mapping technique to convert the sequential loop to a machineindependent high-level intermediate code; (3) Converting the machine-independent intermediate code to that of the target machine; (4) Feed the intermediate code of the target machine to the backend of the compiler of the target machine to obtain the optimized assembly code of the target DSP processor We have conducted a series of experiments using the popular TIC62 as the source DSP and SC140 as the target DSP. Six DSP kernel programs have been selected for the experiments. To verify the validity of the converted code, we have used a simulator to compare the results of various steps in the conversion process. All the results of our experiments show that the converted assembly code of target DSP processor are correct with comparable performance to the assembly code directly generated by compiling the source code with the optimizing compiler of the target machine.

We investigate a new pattern mapping method to convert the assembly code between two VLIW digital signal processors. The method is so named because the pattern of the code is kept unchanged during the conversion process in order to manage complexity. As a case study, we first manually convert the assembly code of a typical DSP application from a Texas Instruments TIC62, the source processor, to a high level intermediate code. We then feed the intermediate code to the SC140 compiler backend to generate the assembly code of the target SC140 processor, which is executed on the SC140 simulator. The result thus obtained compares favorably with that obtained directly by compiling and executing the C code on the SC140 system in terms of both validity and total execution cycles.

It is a challenge to convert the existing conventional DSPs' assembly code to that of VLIW DSPs'. We propose a new code migration method, which performs semantically equivalent code conversion. Key issues such as semantics of the conventional DSP code, specialized addressing modes and different data types are discussed.

This paper proposes the possibility of reuse of the existing optimized DSP code on a scalable high-performance VLIW DSP processor. Since loops are the critical paths in most DSP applications, we focus on issues related to loop optimization. In our approach, we first perform a loop alignment transformation on the source level; we then reuse the existing optimized loop code on the assembly level. The approach is highly portable because it is independent of DSP hardware details. It can be used directly by a DSP programmer on the source level and/or by a DSP compiler designer to implement independent optimization modules.

Performance measurement is essential for the users and manufacturers of DSP processors. However, due to the diversity and complexity of DSP architectures and the large overhead of DSP compilers, metrics that effectively and objectively measure and compare the performance of various DSP processors from different manufacturers remain elusive. We introduce in this paper a new concept of instruction group where instructions in an instruction group are executed in parallel. Among other parameters such as the total execution time and the instruction count, we define the instruction group count of a DSP program as a new metric and study the impact of the group count as one of the parameters on various performance aspects of a DSP processor. Extensive experiments have been conducted by compiling the C code of a collection of DSP kernels and application programs and then executing the compiled code on several popular DSP processors. Both static and dynamic experimental data are analyzed and discussed in the context of the architecture of the DSP processors and the efficiency of the compilers.

The performance of current C compilers for DSP is almost unacceptable. One of the most important reasons is the lack of implementing software pipelining. This paper presents a remedy called source-level loop optimization. DSP programmers can use source-level loop optimization first then input its result to the DSP compiler to obtain better assembly code. The implementation of source-level loop optimization is easier than that of software pipelining. The preliminary result with the DSP compiler-challenge C code shows that source-level loop optimization is a portable and efficient approach. The detailed method and working examples are presented.

To solve efficiently pointer aliasing problem and make the potential instruction-level parallel speedup possible, the new run-time pointer aliasing disambiguation method, named SHPTD (software/hardware run-time disambiguation) was proposed. The SHRTD method allows function units to execute NOPs for postponing the incorrect memory load operation and its successive operation, and assure the consistency of the execution sequence of all postponed operations, and the sequence of function unit which executes NOPs and the number of NOPs must be determined during compiling. The SHRTD can be used for irreversible code, has very limited compensation code space and no serious rerollability problem.

How to select an architecture which has better performance cost ratio, how to design a balanced architecture which can fit most DSP programs and how to generate a custom-fit DSP processor are important topics now. This paper presents a novel methodology based on source-level loop optimization which can avoid expensive retargetable compiler and simulator, and exhaustive experiments.