Communication latency problems are universal and have become a major performance bottleneck as we scale in big data infrastructure and many-core architectures. Specifically, research institutes around the world have built specialized supercomputers with powerful computation units in order to accelerate scientific computation. However, the problem often comes from the communication side instead of the computation side. In this paper we first demonstrate the severity of communication latency problems. Then we use Lattice Quantum Chromo Dynamic (LQCD) simulations as a case study to show how value prediction techniques can reduce the communication overheads, thus leading to higher performance without adding more expensive hardware. In detail, we first implement a software value predictor on LQCD simulations: our results indicate that 22.15% of the predictions result in performance gain and only 2.65% of the predictions lead to rollbacks. Next we explore the hardware value predictor design, which results in a 20-fold reduction of the prediction latency. In addition, based on the observation that the full range of floating point accuracy may not be always needed, we propose and implement an initial design of the tolerance value predictor: as the tolerance range increases, the prediction accuracy also increases dramatically.

Configuring and executing application across multiple clouds is a challenging task due to the various terminologies used by cloud providers to describe their services and features. Likewise, the services are regularly offered at different levels of abstraction, such as infrastructure-as-a-service (IaaS) and platform-as-a-service (PaaS). While IaaS services provide low-level access to the infrastructure, PaaS services enable the users to delegate the management of the computing environment to the cloud providers. Consequently, at the IaaS level, the users are responsible for managing the computing resources, whereas, at the PaaS level, the users must develop native cloud applications following the constraints defined by the PaaS provider. These two options exist, mostly because the clouds target web applications, whereas users' applications are commonly batch-oriented. Considering how difficult is the task of configuring and executing applications across various clouds, we advocate the use of autonomic systems to do this work automatically. For this purpose, in this paper, we propose and evaluate an autonomic and goal-oriented system. Our system implements self-configuration, self-healing, and context-awareness properties. In addition, it relies on a hierarchical P2P overlay (a) to manage the virtual machines running on the clouds and (b) to deal with inter-cloud communication. Likewise, it depends on a software product line engineering (SPLE) method to enable applications' deployment and reconfiguration at runtime, without requiring pre-configured virtual machine images. Experimental results show that our system frees the users from the duty of configuring and managing the execution of a non-native application on single clouds and over many clouds. In particular, our system tackles the lack of middleware prototypes that can support different scenarios when using simultaneous services from multiple clouds.

The study and design of a very ambitious petaflop cluster exclusively dedicated to Lattice QCD simulations started in early '08 among a consortium of 7 laboratories (IN2P3, CNRS, INRIA, CEA) and 2 SMEs. This consortium received a grant from the French ANR agency in July '08, and the PetaQCD project kickoff took place in January '09. Building upon several years of fruitful collaborative studies in this area, the aim of this project is to demonstrate that the simulation of a 256 x 1283 lattice can be achieved through the HMC/ETMC software, using a machine with efficient speed/cost/reliability/power consumption ratios. It is expected that this machine can be built out of a rather limited number of processors (e.g. between 1000 and 4000), although capable of a sustained petaflop CPU performance.The proof-of-concept should be a mock-up cluster built as much as possible with off-the-shelf components, and 2 particularly attractive axis will be mainly investigated, in addition to fast all-purpose multi-core processors: the use of the new brand of IBM-Cell processors (with on-chip accelerators) and the very recent Nvidia GP-GPUs (off-chip co-processors). This cluster will obviously be massively parallel, and heterogeneous. Communication issues between processors, implied by the Physics of the simulation and the lattice partitioning, will certainly be a major key to the project.

The gap between processors and main memory performance increases every year. In order to overcome this problem, cache memories are very useful. Compile-time program transformations can signi cantly improve the performance of the cache. To apply most of these transformations, the compiler requires a precise knowledge of the locality of the di erent sections of the code, both before and after being transformed. This report describes analysis techniques aiming at providing explanations to performance of a program, as far as the cache is concerned. General Reference Windows (GRWs) gives a measure of the amount of memory references that are live at any point in the execution of the program, that is, references previously loaded into the cache, and to be reused later on. Clearly if the size of the window exceeds the capacity of the cache at some point, then cache misses are due to occur at this point. GRWs can be expressed through sets of linear inequations, which one can view as polyhedra, whose number of integer points have to be computed; for this task we can use the Polylib library. The rst part of this reports explains the di culties encountered in computing the GRWs, which improvements are required from the Polylib, and how we plan to circumvent the problems. We also describe a dynamic computation of GRWs, that may be an alternative complementing the static analysis. The second part concerns Cache Miss Equations (CME) which allow to obtain an analytical and precise description of the cache memory behavior for loop-oriented codes. Describing the cache behavior by means of diophantine equations allows us to use mathematical techniques to obtain cache misses. Unfortunately, a direct solution of the CME is computationally intractable due to its NP-hard nature. In this work we present e ective techniques that exploit some properties of the particular polyhedra generated by CME. Such techniques reduce the complexity of the algorithm to solve CME from exponential to polynomial, which results in a signi cant speed-up when compared with traditional methods. We propose a fast and accurate approach to estimate the solution of the CME, which is based on the use of sampling techniques. Statistical techniques allow us to approximate the absolute miss ratio of each reference by analyzing a small subset of the iteration space. The size of the subset, and therefore the analysis time, is determined by the accuracy selected by the user. The results show that only a few seconds are required to analyze most of the SPECfp benchmarks with an error smaller than 0.01. MHAOTEU: Project No 24942

Pervasive video processing in future Ambient Intelligence environments sets new challenges in embedded system design. In particular, very high performance requirements have to be combined with the constraints of deeply embedded systems, frequently changing operating modes, and low-cost, high-volume production. By leveraging upon the key properties of the application domain, we devised a computation model, a hardware template, and a programming approach which provide a natural mapping from application requirements to a complete system solution. Our approach enables the direct exploitation of concurrency and regularity in achieving the combined challenge of adaptability, performance, and efficiency.

In compilers register allocation in loops is usually performed by coloring a corresponding circular-arc graph. Generally, the problem of finding the chromatic number of circular-arc graphs is known to be NP-complete. Thus, approximation algorithms should be considered. In this paper we propose heuristics based on decomposition of a so called meeting graph into a set of circuits. We explain the importance of the meeting graph for our solutions and prove properties of our decomposition of the graph into circuits. We derive inequalities relating the number of circuits in the decomposition to the size of the maximum stable set of chords, and present experimental results. Finally, we discuss the quality of our heuristics for circular-arc graph coloring.

Programming specialized processors requires solving complex resource constrain- ts related to the underlying architecture. Although one instruction of the Philips TriMedia VLIW processor can issue five parallel operations, each category of operations can only be allocated to a subset of the five available slots. In this report we show how these restrictions can be translated into constraints based on reservation tables. This allows us to directly apply all classical algorithms for code generation and optimizatio- n. An important byproduct is that dynamic processes, such as «on the fly» code generation, are made tractable, even though resource constraints are strongly static.

This paper presents an overview of the activities carried out within the second year of the ESPRIT project OCEANS whose objective is to combine high and low-level optimisation approaches within an iterative framework for compilation. In this paper we discuss our approach to iterative compilation.

this paper, we present a method for representing such placement constraints using the concept ofresources and reservation tables. In our approach, conict-free placement congurations are modelled usingreplicated virtual resources, and the standard methods for manipulating reservation tables are used to checkthe feasibility of a slot assignment. We present a formulation of the slot assignment problem which is thenmapped to a resource-based model, we demonstrate the equivalence of both...

: This report deals with the interaction between instruction schedulingand register allocation, in the case of straight line code and in the case ofloops. This problem is at the heart of code optimization in microprocessors withinstruction-level parallelism. Usual solutions use heuristics based on a decoupledapproach. We propose here a formulation by linear integer programming, thatallows dependence, resource and register constraints to be integrated in the sameframework . By varying the...

This work addresses the problem of scheduling a basic block of operations on a multiple instruction-issuing processor. We show that integrating register constraints into operation sequencing algorithms is a complex problem in itself. Indeed, while scheduling a forest of unit time operations on a processor with $P$ parallel instruction slots can be solved in polynomial time, the problem becomes NP-hard when $P$ is unbounded but only $R$ registers are available. As a result we have devised a concise integer linear programming formulation of this scheduling problem that accounts for both register and instruction issuing constraints. This allows the use of off-the-shelf routines to find optimum solutions, which can then be compared with the results obtained by polynomial-time heuristics. Two such heuristics are given, and their combined results are shown to be optimal in 99.5% of the cases for trees of height at most 6. A byproduct of these experiments is to show that our integer programming formulation is quite practical as it can find an optimum solution for a tree of height 6 in roughly 0.1 seconds on a sparc workstation.

Software pipelining is an efficient instruction-level loop scheduling technique, but existing software pipelining approaches have not been widely used in practical and commercial compilers. This is mainly because resource constraints and the cyclic data dependencies make software pipelining very complicated and difficult to apply. In this paper we present a new perspective on software pipelining in which it is decomposed into two subproblems-one is free from cyclic data dependencies and can be effectively solved by the list scheduling technique, and the other is free from resource constraints and can be easily solved by classical polynomial-time algorithms of graph theory. Based on this new perspective, we develop a new instruction-level loop scheduling approach, call DEcomposed Software Pipelining (DESP).

One major point in loop restructuring for data locality optimization is the choice and the evaluation of data locality criteria. In this paper we show how to compute approximations of window sets defined by Gannon, Jalby, and Gallivan. The window associated with an iterationi describes the “active” portion of an array: elements that have already been referenced before iterationi and that will be referenced after iterationi. Such a notion is extremely useful for data localization because it identifies the portions of arrays that are worth keeping in local memory because they are going to be referenced later. The computation of these window approximations can be performed symbolically at compile time and generates a simple geometrical shape that simplifies the management of the data transfers. This strategy allows derivation of a global strategy of data management for local memories which may be combined efficiently with various parallelization and/or vectorization optimizations. Indeed, the effects of loop transformations fit naturally into the geometrical framework we use for the calculations.

This paper studies the problem of simultaneous register allocation and software pipelining. We present the Register Requirement Graph to dynamically reflect the register requirement during software pipelining and develop a Register-Pressure-Sensitive (RPS) scheduling technique. Three algorithms—RPS without spilling, RPS with spilling and software pipelining with a limited number of registers—are proposed. The preliminary experimental results show the efficiency of the three algorithms.

This paper uses timed Petri net to model and analyze the problem of instruction-level loop scheduling with resource constraints, which has been proven to be an NP complete problem. First, we present a new timed Petri net model to integrate functional unit allocation, register allocation and spilling into a unified theoretical framework. Then we develop a state subgraph, called Register Allocation Solution Graph, which can effectively describe the major behavior of our new model. The main property of this state subgraph is that the number of all its nodes is polynomial. finally we present and prove that the optimum loop schedules can be found with polynomial computation complexity, for almost all practical loop programs. Our work lightens a new idea of finding the optimum loop schedules.

Trace software pipelining is a novel global software pipelining technique. It can exploit instruction-level parallelism across all iterations of a loop by compacting the original loop body with any global loop-free code scheduling technique. The resulting loop is called a trace software pipelined (TSP) code, which can be executed directly with a special architectural support or be transformed into a globally software pipelined loop for the current VLIW and superscalar processors.