Based on a recent pre-bond TSV probing technique, this paper proposes an iterative greedy procedure to sort the order of test sessions for reducing pre-bond TSV test time. We then combine that session sorting procedure with two existing methods to develop a 3-Step test time Optimization Simulator named “SOS3”. SOS3 consists of an ILP (integer linear programming) model for session generation, the greedy procedure for session sorting, and a TSV identification algorithm for early test termination. Experiments are done for various TSV networks and two observations are made. First, session sorting plays an important role within SOS3 as it helps to further reduce pre-bond test time expectation and thus reduces pre-bond TSV test cost. Second, SOS3 as a framework greatly speeds up the pre-bond TSV test.
Most processors employ hardware data prefetching to hide memory access latencies. However the prefetching requests from different threads on a multi-core processor can cause severe interference with prefetching and/or demand requests of others. The data prefetching can lead to significant performance degradation due to shared resource contention on shared memory multi-core systems. This paper proposes a thread-aware data prefetching mechanism based on low-overhead run-time information to tune prefetching modes and aggressiveness, mitigating the resource contention in the memory system. Our solution has two new components: 1) a filtering mechanism that informs the hardware about which prefetching requests can cause shared data invalidation and should be discarded, and 2) a self-tuning prefetcher that uses run-time feedback to adjust each thread's data prefetching mode and arguments. On a set of parallel benchmarks, our thread-aware data prefetching mechanisms improve the overall performance of 64-core system by 11% and reduce the energy-delay product by 13% over a multi-mode prefetch baseline system with a two level cache organization and a conventional MESI-based directory coherence protocol. We compare our approach to the feedback directed prefetching (FDP) technique and find that it provides better performance on multi-core systems, while reducing the energy delay product.
Stochastic computing (SC) is an approximate computing technique that represents data by probabilistic bit-streams called stochastic numbers (SNs). Arithmetic operations can be implemented at very low cost by means of SC. To achieve acceptable accuracy, interacting SNs must usually be statistically independent or uncorrelated. Correlation is poorly understood, however, and is a key problem in SC because of its impact on accuracy and the high cost of correlation-reducing logic. In this paper we analyze and quantify the role of correlation in stochastic circuit design. We use an algebraic framework based on probabilistic transfer matrices (PTMs) to analyze correlation-induced errors. We compare two systematic correlation-reducing methods, regeneration and isolation. Regeneration introduces new (pseudo) random sources to re-randomize SNs, while isolation uses delays (D flip-flops) to derive multiple independent SNs from a single random source. We present bounds on accuracy loss due to isolator insertion and compare its hardware cost to that of regeneration. We conclude that the isolation method can offer significant cost advantages in reducing correlation errors.
Extreme ultraviolet (EUV) lithography is one of the most promising next-generation lithography technologies, while chemical mechanical polishing (CMP) is the key planarization process for improving chip surface topography. The two techniques are highly related to layout pattern distribution and require different (even conflicting) distributions for EUV flare and CMP variation optimization to achieve better yields. Placement is a critical stage for controlling layout pattern distribution. In this paper, we propose the first work of simultaneous EUV flare-and CMP-aware placement to address the conflicting pattern distribution requirements with the two techniques. We present a sigmoid distribution model to reduce EUV flare effects and a metal-aware pin model to improve metal distribution. The two models are incorporated into a non-linear analytical optimization framework to achieve desired placement solutions. Experimental results show the effectiveness and efficiency of our proposed method.
Networks-on-Chips (NoCs) are experiencing escalating susceptibility to wear-out and reduced reliability, with the risk of becoming the key point of failure in an entire multicore chip. Aiming towards seamless NoC operation in the presence of faulty communication links, in this paper we propose Hermes, a highly-robust, distributed and lightweight fault-tolerant routing algorithm, whose performance degrades gracefully with increasing faulty link counts. Hermes is a deadlock-free hybrid routing algorithm, utilizing load-balancing routing on fault-free paths to sustain high-performance, while providing pre-reconfigured escape path selection in the vicinity of faults. Additionally, Hermes identifies non-communicating network partitions in scenarios where faulty links are topologically densely distributed. An extensive experimental evaluation, including utilizing traffic benchmarks gathered from full-system chip multi-processor simulations, shows that Hermes improves network throughput by up to 3× when compared against prior-art.
Energy efficiency has always been an important design criterion for portable embedded systems. To compensate for the shortcomings of electrochemical batteries such as low power density, limited cycle life, and the rate capacity effect, supercapacitors have been employed as complementary power supplies for electrochemical batteries, i.e., hybrid power supplies comprised of batteries and supercapacitors have been proposed. In this work, we consider a portable embedded system with a hybrid power supply and executing periodic real-time tasks. We perform system power management from both the power supply side and the power consumption side to maximize the system service time. Specifically, we use feedback control for maintaining the supercapacitor energy at a certain level by regulating the discharging current of the battery, such that the supercapacitor has the capability to buffer the load current fluctuation. At the power consumption side, we perform task scheduling to assist supercapacitor energy maintenance. Experimental results demonstrate that the proposed joint optimization framework of task scheduling and power supply control successfully prolongs the total service time by up to 57%.
Given its low power consumption and high density, Phase Change Memory (PCM) has been treated as a promising alternative to DRAM for main memory storage. Multilevel Cell (MLC) PCM outperforms regular single level cell (SLC) PCM with even higher information density, yet requires more accurate control for cell reading and writing. More crucially, the resistance of a MLC PCM cell may drift over time, thus introducing high error rate during cell reading if the quantization thresholds are constant. While previous work tries to adjust the quantization method when reading a cell, its accuracy is still limited due to the inter-cell variations in data age. In this paper, we propose various PCM writing and quantization strategies to improve MLC PCM reliability. Cell quantization accuracy is improved by taking into consideration not only the time information but also inter-cell age variations. Moreover, by making the write strategy be aware of time, the inter-level quantization margin can be guaranteed when the cells exhibit large age variations. This time-aware writing scheme is adaptively applied to maximize achievable benefits. The experimental results show that the proposed writing and reading approaches can effectively reduce the quantization error rate in MLC PCM by 95%.
Non-volatile memory (NVM) technologies support both byte addressability (like DRAM) and non-volatility (like disks). This characteristic makes it feasible for NVM to be employed at any layer of the memory hierarchy including CPU cache, main memory, file cache, storage, and hybrid memory. In this paper, we explore new challenges and opportunities that arise when NVM is introduced as a file cache in the memory hierarchy. One opportunity is that cache does not require long-term non-volatility since data are replaced when working sets are changed. This feature is well matched with NVM, which has limited retention time. In addition, the retention time of NVM is inverse proportional to the write latency, giving a chance to optimize the write performance. However, the limited retention time raises a new challenge that it may cause the hit ratio reduction and lead to cache performance degradation. To tackle this challenge, we propose a new inter-reference gap (IRG) based cache management scheme that writes data with different retention times according to their IRGs. Our proposal builds on the fact that block accesses of typical workloads show unique and regular patterns in terms of access intervals. Experimental results show that our scheme enhances system performance by up to 42% (33% on average), compared with the conventional LRU based cache management scheme.
Floating point multiplication is one of the most frequently used arithmetic operations in a wide variety of applications, but the high power consumption of the IEEE-754 standard floating point multiplier prohibits its implementation in many low power systems, such as wireless sensors and other battery-powered embedded systems, and limits performance scaling in high performance systems, such as CPUs and GPGPUs for scientific computation. This paper presents a low-power accuracy-configurable floating point multiplier based on Mitchell's Algorithm. Post-layout SPICE simulations in a 45nm process show same-delay power reductions up to 26X for single precision and 49X for double precision compared to their IEEE-754 counterparts. Functional simulations on six CPU and GPU benchmarks show significantly better power reduction vs. quality degradation trade-offs than existing bit truncation schemes.
DRAM cells are leaky and need periodic refresh, which hurts system performance and consumes additional energy. With DRAM scaling towards sub-20nm process technology, we expect a significant portion of DRAM cells become weak cells and require a higher refresh rate, resulting in even higher refresh overhead. A possible solution is to selectively refresh those weak cells using a higher frequency but still refresh the majority at the nominal rate. However, how to provide a multi-rate DRAM refresh scheme is not straightforward. Previous work on this topic was built on an obsolete refresh framework and was incompatible to modern DRAM standards, making it challenging to be adopted in practice. In this work, we propose ProactiveDRAM, a novel scheme that allows DRAM proactively guides the timing of weak cell refresh management and reuses memory controllers' capability in command scheduling. ProactiveDRAM offers a smart retention-aware refresh on the DRAM row granularity, and more importantly, it can be built atop any modern DRAM architecture. Our simulation results show that ProactiveDRAM can handle 1% (or even 10%) weak row population with negligible performance and energy overhead1.
Process variation in advanced CMOS processes is an increasingly important influence in test efficiency, design optimization and yield learning. Yet, there is no efficient test process to assist designers to categorize chips for analyzing the influence of variation on their respective objectives. In this paper, we propose a test process and an analysis method with multiple clocks. Each chip is first tested with selected paths on multiple clocks (smaller than target chip clock). And the test results of outputs on selected paths are recorded and further used as a signature to determine the class of which the chip belongs to. As an application, we use the proposed scheme to sort chips into different categories and assign a supply voltage configuration for each category to fix chip timings. In experiments, results show that testing with one or two clocks, the method can obtain chip yields of 88-99% (original yield is 9-34%) with an increase of 4-25% nominal dynamic powers, while full-swing voltage setup would require 50% increase of powers.
Field Programmable Gate Arrays, or FPGAs, allow designers to implement hardware designs using hardware description languages (HDLs). This type of designs have been gaining significant popularity since improvements in clock frequencies, of high-end CPUs, have started to level off and other alternatives have been explored to accelerate computations. However, traditional HDLs lack a number of modern facilities and a rich ecosystem to express and test designs, which severely restricts the productivity of designers. In this paper, we propose ScalaHDL, an open-source domain-specific language (DSL) built on top of Scala, that enables designers to describe algorithms using a multi-paradigm programming language, and generate the required Verilog code to implement such systems. In addition, these designs can be simulated so that values can be tested programmatically using unit-tests. With ScalaHDL, designers can also leverage the rich and mature ecosystems provided by Java and Scala.
To mitigate the significant main memory access latency in modern chip multiprocessors, multi-level on-chip caches are used to bridge the gap by retaining frequently used data closer to the processor cores. Such dependence on the last-level cache (LLC) has motivated numerous innovations in cache management schemes. However, most prior works focus their efforts on optimizing cache miss counts experienced by applications, irrespective of the interactions between the LLC and other components in the memory hierarchy such as the main memory. This results in sub-optimal performance improvements, since reducing miss rates does not directly translate to increased IPC performance.In this paper, we show that in addition to the recency information provided by the cache replacement policy, post eviction reuse distance (PERD) and main memory access latency cost are useful to make better-informed eviction decisions at the LLC. We propose ReMAP, Reuse and Memory Access Cost aware eviction policy, that takes reuse characteristics and memory access behavior into consideration when making eviction decisions. ReMAP achieves higher performance compared to prior works. Our full-system simulation results show that ReMAP reduces the number of misses of SPEC2006 applications by as much as 13% over the baseline LRU replacement and by an average of 6.5% while MLP-aware replacement and DRRIP reduce the miss counts by -0.7% and 5% respectively. More importantly, ReMAP achieves an average of 4.6% IPC performance gain across the SPEC2006 applications while MLP-aware replacement and DRRIP see only 1.8% and 2.3% respectively.
To ensure functional correctness, conventional chip implementation methodology signs off the SOC design at extreme process, voltage and temperature (PVT) conditions. At the 20nm node and beyond, the back end of line (BEOL) layers have become major sources of variation, which must be accounted for by signoff at various BEOL corners. Conventional signoff methodology uses extreme BEOL corners, in which all BEOL layers are skewed to the worst-case condition (e.g., all BEOL layers have the worst parasitic capacitance). However, such a BEOL condition is very pessimistic because the probability of having all BEOL layers skew towards the worst-case condition simultaneously is extremely small. Such pessimism results in longer chip implementation schedules and poorer design quality. In this paper, we propose a signoff methodology with tightened BEOL corners to recover the pessimism incurred by the conventional BEOL corners. This approach is based on the observation that most timing-critical paths use different BEOL layers. When the variations of BEOL layers are not fully correlated, the BEOL-induced timing variation is much smaller due to averaging of random variations. Our experimental results show that by using tightened BEOL corners, we can reduce timing-violation paths by up to 100% and improve the WNS and TNS by up to 101ps and 53ns, respectively.
Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. We present an efficient built-in self-test (BIST) architecture for targeting defects in dies and in the interposer interconnects. The proposed BIST architecture can also be used for fault diagnosis during interconnect testing. We present simulation results to validate the BIST architecture and demonstrate fault detection, synthesis results to evaluate the area overhead of the proposed BIST architecture, and fault coverage results to highlight the effectiveness of the proposed technique.
Spin-transfer torque random access memory (STTRAM) is an emerging memory technology with several attractive properties including non-volatility, high density, low leakage, and high endurance. These characteristics make it a potential candidate for replacing SRAM structures on processor chips. This paper presents NVSleep, a low-power microprocessor framework that leverages STT-RAM to implement fast checkpointing that enables near-instantaneous shutdown of cores without loss of the execution state. NVSleep stores almost all processor state in STT-RAM structures that do not lose content when power-gated. Memory structures that require low-latency access are implemented in SRAM and backed-up by “shadow” STT-RAM structures that are used to implement fast checkpointing. This enables rapid shutdown of cores and low-overhead resumption of execution, which allows cores to be turned off frequently and for short periods of time to take advantage of idle execution phases and save power. We present two implementations of NVSleep: NVSleepMiss which turns cores off when last level cache misses cause pipeline stalls and NVSleepBarrier which turns cores off when blocked on barriers. Evaluation of a simulated 64-core system shows average energy savings of 21% for NVSleepMiss for SPEC2000 benchmarks and 34% for NVSleepBarrier in high barrier count multi-threaded workloads from PARSEC and SPLASH2 benchmarks.
Phase change memory (PCM) has demonstrated great potential as an alternative of DRAM to serve as main memory due to its favorable characteristics of non-volatility, scalability and near-zero leakage power. However, the comparatively poor endurance of PCM largely limits its adoption. Wear leveling strategies targeting to even write distributions have been proposed at different granularities and on various memory hierarchies for PCM endurance enhancement. Write operations are distributed across the memory through migrating data from heavily written locations to less burdened ones, which is usually guided by counters recording the number of writes. However, evenly distributing writes at a coarse granularity cannot deliver the best endurance results as write distributions are highly imbalanced even at the bit level. In this work, we propose a near-zero-cost bit-level wear leveling strategy to improve PCM endurance. The proposed technique can be combined with various coarse-grained wear leveling strategies. Experiment results show 102% endurance enhancement on average, which is 34% higher than the most related work, with significantly lower storage, performance and energy overheads.
A modern GPU processor consumes several times power of a multi-core CPU and delivers a much higher processing throughput. Researchers propose various architectural innovations to improve its energy efficiency. We observe that different streaming processors (SMs) in a GPU tend to exhibit very similar behavior for many GPU workloads. If multiple SMs can be grouped together and work in synchronous manner, it is possible to save energy by sharing the front-end in the SM pipeline including the instruction fetch, decode and schedule units. For efficient flow control and program correctness, the proposed architecture can identify unfavorable conditions and ungroup the SMs when necessary. However, sharing pipeline front-end between multiple SMs brings architectural challenges. In this paper, we show our design, implementation and evaluation for such an architecture. Detailed experiment results manifest 33.7% front-end and 6.8% total GPU energy reduction can be achieved.
The use of STT-RAM as on-chip caches has been widely studied. However, existing works focused mainly on single-level cell (SLC) design while the potential of multi-level cell (MLC) STT-RAM has not yet been fully explored. It is expected that MLC STT-RAM can achieve 2× the storage density of SLC and thus improves system performance. Unfortunately, at the device level, the two-step read/write scheme introduces performance and energy overhead. In this paper, we propose an architectural design to dynamically reconfigure the cache block size for a MLC STT-RAM last-level cache. Our approach place certain hot data chunks in smaller blocks so as to benefit from the lower latency and energy, while keeping the rest in larger blocks to maintain an overall hit rate. Experiment shows that our strategy reduces the performance and energy penalty of MLC STT-RAM caches with a slightly higher miss rate. On average, IPC is increased by 4.6% while energy consumption is reduced by 23.5% compared to the conventional MLC STT-RAM cache.
Power gating is a very effective method in reducing the leakage energy during the standby mode in VLSI circuits at the cost of increased circuit delay. This method has been well studied and widely used for circuits fabricated by using traditional CMOS technology nodes operating at super-threshold supply voltage regime. However, for advanced technology nodes with small feature sizes and low supply voltages, the propagation delay becomes very sensitive to the high process-induced variations. Therefore, this paper first analyzes how the circuit delay depends on the size of the sleep transistor under the process-induced variation for the 7nm gate length FinFET technology. Then a joint optimization problem is formulated to minimize the total energy consumption, while both supply voltage and sleep transistor size are considered as optimization variables. A near-optimal heuristic is presented to solve the optimization problem and determine the energy-optimal supply voltage and sleep transistor size. Experimental results based on HSPICE simulations show that more than 98% energy reduction for applications with relaxed deadline constraints after applying the joint optimization technique, compared to FinFET circuits without using the power gating method.
