High-performance and highly-stable oxide transistors are essential for the development of advanced memory devices and monolithic 3D integration. In this study, high-k ultra-thin ITO transistor with 45 min air annealing process is demonstrated, which achieves a mobility of 86.5 cm2/V center dot s, a subthreshold swing (SS) of 80.4 mV/ decade, a minimal hysteresis window of-0.15 V, and a low gate leakage current of 5.5 pA. Furthermore, the 45- min air-annealed ITO transistors also exhibit remarkable stability under negative and positive bias stress (NBS and PBS) conditions. In addition, optimizations in subthreshold swing (SS), and stability is enhanced with increase in annealing time, but the slight mobility degradation is caused by prolonged annealing. The underlying mechanism is revealed by X-ray photoelectron spectroscopy (XPS) analysis and Line-Energy Dispersive Spectroscopy (EDS). The results indicate that the reduction of oxygen vacancies, which mainly occur in HfO2, and at the surface of ITO contributes significantly to the improved electrical performance and stability of ultra-thin ITO transistor. Finally, a depletion-mode inverter cell based on the air-annealed ITO transistor is demonstrated, highlighting the potential of ITO transistors in the field of integrated circuits (ICs).

A unique episode in the transregional connections of Buddhism is illustrated through the figures of Ruan Ziyu (1079–1102) and Liang Cineng (1098–1116). Since at least the Song dynasty, Huineng (638–713), the Sixth Patriarch of Chan Buddhism, has been a revered figure in Guangdong province of China, resulting in the formation of numerous stories and legends. In the Sihui region, near the urban hub called Zhaoqing, Ruan and Liang emerged as notable disciples of Huineng, reputed to have had spiritual encounters with the Sixth Patriarch and attained Buddhahood. Known as the “Ruan Buddha” and the “Liang Buddha”, they were venerated by the Sihui people during times of droughts, turmoil, and health crisis. Over time, they became integral to Sihui identity and spread to Southeast and South Asia, particularly as people emigrated from the region in the late nineteenth century. This article examines the various stories about Ruan and Liang that circulated in Sihui and how the two buddhas have been venerated, without many links to Huineng or Buddhism, in Malaysia and India. It highlights the significance of local adaptations of Buddhist figures in transregional contexts.

With the development of high-resolution ADCs (>13b) leveraging the SAR topology, the pursuit of power efficiency in ADC design continues to make remarkable strides [1]–[5]. However, as the capacitance of the capacitive DAC (CDAC) increases to satisfy the kT/C noise specification, excessive driving pressure is posed on the front-end input buffer. Furthermore, a separate higher supply voltage is typically demanded for the driver to accommodate the input swing while maintaining the linearity requirement. The increasing load and wide supply voltage often make the power consumption of the ADC core overwhelmed by the power consumption of the driving buffer, presenting a bottleneck in achieving an overall energy-efficient system. Loop-embedded buffer architectures have been explored in prior arts to reduce the linearity requirement of the buffer while easing the driving pressure of the system [2], [6]–[8]. Rail-to-rail signal swing is achieved in [7] with a dedicated capacitive level shifting bias scheme. Besides, a rail-to-rail high-linearity input buffer using a predictive level shifting technique is proposed in [3], but careful tuning of the predictor is necessary for the targeted performance.

To address the “memory wall” bottleneck in traditional von Neumann architectures and meet the growing demand for energy-efficient edge AI inference, this paper proposes an SRAM-based hybrid Computing-in-Memory (CIM) architecture that integrates analog and digital computing units. By combining the high energy efficiency of Analog CIM (ACIM) in lowprecision parallel operations (such as convolution) with the high accuracy of Digital CIM (DCIM) in precision-critical tasks (such as activation functions), this architecture achieves a balanced trade-off between efficiency and accuracy. The core innovations of this architecture lie in three aspects: hardware-aware design, optimized dataflow scheduling, and integration of security mechanisms. At the hardware level, it is customized for edge AI operators like convolution, fully leveraging SRAM’s CMOS compatibility and parallel computing capabilities. For dataflow scheduling, it adopts sliding windowaware input caching and a “compute-while-update” pipelining mechanism to significantly reduce data movement overhead. Additionally, it incorporates Advanced Encryption Standard (AES) operations into the CIM framework to ensure the security of data processing. Experimental validation based on YOLO model inference shows that compared with traditional designs, this architecture reduces data movement energy consumption by 37% and computation latency by 29%, providing a robust low-power solution for edge AI applications that require both high energy efficiency and secure operation.

This work presents a 2-mW 70.7-dB SNDR 200-MS/s pipelined-successive-approximation-register (SAR) analog-to-digital converter (ADC) with a continuous-time SAR-assisted detect-and-skip (CTDAS) and open-then-close correlated level shifting (OCCLS). In the first-stage SAR ADC, we propose using the continuous-time SAR (CTSAR) as the coarse SAR ADC in the detect-and-skip (DAS) scheme, thus parallelizing MSB conversion with ADC sampling. Furthermore, in the residue amplifier (RA), an OCCLS technique is proposed, which significantly speeds up the first correlated level shifting (CLS) phase by open-loop amplification and consequently enhances the equivalent open-loop gain at negligible extra time cost. An on-chip background self-detect-and-cut loop is used for the OCCLS to attain a PVT-robust high equivalent open-loop gain. For RA implementation, a hybrid static-floating ring-amp structure is adopted to improve the noise performance while fitting in well with the OCCLS scheme. Thanks to the proposed techniques, the 22-nm prototype achieves 70.7-dB SNDR under 200 MS/s while consuming only 2.0 mW from a 0.9-V supply. It measures 177.7-dB FoMs, which is the highest among ADCs with equivalent or higher sampling rates.

Electrocardiography (ECG) has emerged as a ubiquitous diagnostic tool for the identification and characterization of diverse cardiovascular pathologies. Wearable health monitoring devices, equipped with on-device biomedical artificial intelligence (AI) processors, have revolutionized the acquisition, analysis, and interpretation of ECG data. However, these systems necessitate AI processors that exhibit flexible configuration, facilitate portability, and demonstrate optimal performance in terms of power consumption and latency for the realization of various functionalities. To address these challenges, this study proposes an instruction-driven convolutional neural network (CNN) processor. This processor incorporates three key features: (1) An instruction-driven CNN processor to support versatile ECG-based application. (2) A Processing element (PE) array design that simultaneously considers parallelism and data reuse. (3) An activation unit based on the CORDIC algorithm, supporting both Tanh and Sigmoid computations. The design has been implemented using 110 nm CMOS process technology, occupying a die area of 1.35 mm2 with 12.94 µW power consumption. It has been demonstrated with two typical ECG AI applications, including two-class (i.e., normal/abnormal) classification and five-class classification. The proposed 1-D CNN algorithm performs with a 97.95% accuracy for the two-class classification and 97.9% for the five-class classification, respectively.

Localizing and identifying sound sources simultaneously through binaural cues is a crucial ability of humans, which facilitates our perception of complex surrounding scenes. Brain-inspired Spiking Neural Network (SNN) offers an energy-efficient and event-driven paradigm thus it is highly suitable for simulating the signal processing of such perceptions in organisms. Despite recent progress, most existing approaches in SNNs solely focus on a single task, disregarding the broad practicality of multitasking, or fail to consider the complementary features from audio modality for explicit enhancement. Inspired by the biological information sharing within multiple tasks, in this study, we propose a powerful multi-feature oriented sound source localization and classification framework based on SNNs, namely SpikSLC-Net. Specifically, we design a novel Spiking Hybrid Attention Fusion (SHAF) mechanism that incorporates spiking self-attention modules and spiking cross-attention modules, which can effectively capture temporal dependencies and align relationships among diverse features. Then, considering the vanilla layer normalization (LN) requires dynamic calculation during runtime and involves a significant amount of floating-point operations, we present a unique training-inference-decoupled LN method (DSLN) for SNNs. To further aggregate the multi-scale audio information, two task-specific heads are introduced for the final direction-of-arrival (DoA) estimation and event class prediction. Experimental results demonstrate that the proposed SpikSLC-Net achieves state-of-the-art performance with only 2 time steps on SLoClas dataset.

Spiking neural network (SNN), a bio-inspired neuron network, utilizes a learning rule named spike-timing-dependent plasticity (STDP) to achieve high-performance unsupervised learning. However, it may suffer from catastrophic forgetting when the distribution of new data significantly differs from that of old data. To address this issue, an incremental learning implementation for ship classification is presented in this paper. We develop an incremental learning algorithm based on STDP and corresponding platform. A competitive SNN is built into our algorithm, and add-STDP is utilized to update the weights of network for efficient learning. To enhance learning performance, we incorporate weight decay. And to avoid catastrophic forgetting, we incorporate data replay. The corresponding learning platform consists of the FPGA Zynq 7100 and the STDP neuromorphic prototype chip, and our algorithm is executed on the chip. We evaluate the ship classification task on our platform, which demonstrates the superior potential of our on-chip implementation for incremental learning.

Low power consumption is a significant advantage of SAR ADCs, while comparator is the main power consumer. In this paper, a progressive calibration method for comparator is proposed, which allows the power consumption of SAR ADC to vary linearly with the sampling rate, and improves the conversion time utilization and SAR ADC speed through the progressive calibration. A 16 bit 1 MSPS SAR ADC with the proposed comparator was design in 0.18um CMOS process. The prototype achieves 93.6db SNDR at 20-kHz input while operating at 1 MS/s and comparator consumes 6.5mW. It was drown in 0.18um CMOS and occupies 0.82mm 2 .

Silicon nitride is widely used in microelectronics technology, photoelectric technology and so on. Common silicon nitride preparation methods include Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Plasma Enhanced Atomic Layer Deposition (PEALD), etc. Among them, the PECVD method has the characteristics of relatively low process temperature and fast film deposition rate. In this work, we have successfully prepared silicon nitride thin films using Ammonia-free PECVD process technology and studied the influence of Radio Frequency (RF) power and $\mathbf{SiH}_{4}/\mathbf{N}_{2}$ gas ratio on deposition rate of silicon nitride thin film and get a low deposition rate of 2.59 nm/min.

Wuqian (1922–2010) was one of the most important modern Buddhist masters in the modern history of Sino-Indian Buddhist relations. In his early years, he studied all the major schools of the Buddhist tradition, focusing on Yogācāra philosophy, probably due to Xuanzang’s influence and in alignment with contemporary Buddhist trends. Furthermore, he became one of the few masters from the Central Plains who received systematic training in Tibetan Buddhist tantric rituals. He went to India in the middle of the 20th century. He dedicated his life to the revival of Buddhist thought in India, especially promoting Chinese Buddhism in Calcutta by establishing Buddhist institutions, managing Buddhist sites, organizing Buddhist activities, and building the Xuanzang Temple. In his later years, he devoted himself to facilitating mutual Buddhist exchanges and monastic visits between Buddhist organizations in mainland China, Taiwan, and India. In 1998, he presented two Buddhist relics to the Daci’en Temple in Xi’an. At the beginning of the 21st century, he established the Institute of Buddhist Studies at Xuanzang Temple in Calcutta. He organized the translation of many important Buddhist treatises, again reflecting his intention of following the spirit of Xuanzang to contribute to Chinese Buddhism. His transnational journey manifested that there was an active Asian Buddhist network during the Cold War era, despite various difficulties.

Quantum transport simulation based on first principles has been widely applied to study the transport properties of nanoscale devices. However, such a method is computationally expensive to study large-scale systems, which becomes a key bottleneck in device simulations. To this end, we develop a deep neural network approach to accelerate quantum transport simulations., enabling faster transport calculations while maintaining accuracy for large-scale devices. We studied monolayer Mos2 diodes with different scales as the study system., mapped their atomic structure characteristics to local descriptors as the input of the neural network., and used the non-equilibrium Green's function-density functional theory (NEGF-DFT) method to calculate the electron transmission coefficient of the system as the output of prediction. Our experimental results show that for large-scale devices, quantum transport modeling based on machine learning can achieve acceptable computational efficiency, and our scheme provides a promising solution for breaking the accuracy-efficiency dilemma to achieve large-scale nanodevice simulation.

去殖民主义、去人类中心主义浪潮中兴起的动物史研究,引起了亚洲史学者的注意.在过去20多年中,亚洲研究和亚洲史学者纷纷从人文学科的不同领域转向动物史研究,其中亚洲动物史领域出现了一系列引人注目的成果.这些成果虽不如欧美动物史研究的国际影响深远,却是方兴未艾的史学新趋势,甚至可以说出现了亚洲史研究的"动物转向".亚洲动物史研究虽然面临诸多挑战,但角度和视野的转变带来了新的机遇.特别是全球史兴起后,逐渐与动物史研究结合在一起,出现了不少令人耳目一新的研究成果.

With the continuous development of human society, earthquakes are becoming more and more dangerous to the production and life of human society. Researchers continue to try to predict earthquakes, but the results are still not significant. With the development of data science, sensing and communication technologies, there are increasing efforts to use machine learning methods to predict earthquakes. Our work raises a method that applies big data analysis and machine learning algorithms to earthquakes prediction. All data are accumulated by the Acoustic and Electromagnetic Testing All in One System (AETA). We propose the multi-station Principal Component Analysis (PCA) algorithm and extract features based on this method. At last, we propose a weekly-scale earthquake prediction model, which has a 60% accuracy using LightGBM (LGB).

孟加拉文化是以孟加拉语为母语的孟加拉国和印度西孟加拉邦的民族区域文化,其若干典型文化现象包括语言、服饰、节庆等构成当代孟加拉文化的全球化与本土性特征.在全球化视野下,文化研究的理论观点和方法有助于分析阐释这些文化现象在当代孟加拉文化变迁中的作用和影响.后殖民文化理论的"杂交"学说及"第三空间"概念下的探讨显示出,以多元、包容、融合为特点的当代孟加拉文化及其认同在全球化进程中表现出本土文化特色的强大生命力,其在接受和融汇外来文化的过程中也在不断丰富自己的内涵.虽然部分学者担心的全球文化同质化及后殖民国家在地文化消失的状况在孟加拉地区未见显现,但全球化对本土文化的冲击是不能回避的现实问题.如何在"人类命运共同体"建设中维护各民族文化的特质性,是人们面临的新的历史课题.

Magnetic Random Access Memory (MRAM) is regarded as one of the most promising memory solutions for space missions since the storage mechanism of magnetic tunnel junction (MTJ) as the memory unit is naturally insensitive to the radiation effects. For the application of highly reliable MRAM., the total dose and ion beam radiation responses of a commercial STT-MRAM are evaluated in this work. The results indicate that MTJ is inherently radiation tolerant, while the peripheral circuit exhibits soft errors during ion beam irradiation. We analyze the single event effect (SEE) and look into the soft errors caused by the single event upset (SEU). Finally, considering the special STT-MRAM architecture, possible inducements of the experimental phenomena are discussed.

晶圆-晶圆键合技术突破了传统晶圆平面工艺,但键合晶圆的光刻对准图形及其他辅助图形有特殊的位置摆放和形貌绘制要求,而传统方法进行光刻掩膜版排版费时费力且极易出错.针对该技术挑战,提出一种与传统排版方式不同的整体翻转式排版方法:在面对面晶圆-晶圆(两片)产品排版中,通过"替换-翻转"过程,可以快速有效地一次性解决辅助图形单元形貌和位置的对应翻转,大幅度减少键合产品排版的工作量,降低错误率,有效地缩短产品导入时间周期.

Layout dependence of total-ionizing-dose (TID) response, hot-carrier degradation (HCD), and radiation-enhanced HCD (REHCD) in 65-nm bulk Si nMOSFETs are experimentally investigated in this article. For TID response, the average irradiation-induced V th shift slightly increases by several millivolts with increasing gate-to-active area spacing (SA), which is contrary to the trend previously observed in pMOSFETs. HCD is much more severe in irradiated devices and the average hot-carrier-stress-induced V th shift continuously decrease with increasing SA for both irradiated and unirradiated devices, indicating potential better hot-carrier reliability with larger SA. Finally, layout dependence of REHCD is illustrated. REHCD is enhanced with increasing SA, which may reduce the reliability improvement of irradiated devices with larger SA. These layout dependencies are attributed to larger tensile strain in the channel. The results provide early insights into the layout dependence of TID effects and HCD, highlighting potential concerns on the reliability of devices working in radiation environment.