The use of neural networks for processing X-ray detector data has become a key development trend in high-energy physics and medical imaging. As detector arrays grow, handling the resulting massive data volumes poses significant challenges in terms of system bandwidth and power consumption. To address the bandwidth bottleneck and high analog-to-digital conversion (ADC) power consumption in conventional X-ray imaging systems, we propose an in-sensor computing architecture, SpikeX, for accelerating spiking neural networks (SNN). First, a photon-counting analog front end is directly integrated with pixel-level SNN neurons, enabling the first convolutional layer to be computed using spike signals. This eliminates the need for analog-to-digital conversion, significantly reducing power and bandwidth requirements. Next, an event-driven on-chip SNN accelerator performs efficient temporal inference, enabling an end-to-end pipeline from signal acquisition to image classification. Furthermore, detector non-idealities can be absorbed by the SNN model during training. To systematically investigate these effects, we develop a signal processing algorithm, enabling effective correction of detector non-idealities. To validate the proposed architecture, we implemented the SpikeX using a 180 nm CMOS process, featuring a 28 & times;28 pixel array and 32 Leaky Integrate-and-Fire (LIF) processing units. Simulation results show that, at a clock frequency of 50 MHz, the architecture achieves an energy efficiency of 1.88 TOPS/W, significantly outperforming comparable state-of-the-art designs.

Spiking Neural Networks (SNNs) transmit information via discrete spike events, offering advantages in energy efficiency and computational cost. However, current SNN-based object detectors suffer from limited feature expression and inefficient fusion due to temporal sparsity and the asynchronous nature of spike features. To address these challenges, we propose SpikeGate-YOLO, a spiking object detection architecture optimized for spike-driven processing. Specifically, we introduce the Reparam-Spike Gating (RSG) block to enhance feature expressiveness while maintaining computational efficiency. We also design the Spike Multi-Granularity Difference-aware Feature Harmonizer (SpikeMDFH), which improves multi-scale feature fusion through dynamic attention and biologically inspired gating mechanisms, preserving spike sparsity. Experiments on both the COCO and Gen1 datasets show that SpikeGate-YOLO achieves state-of-the-art results, reaching 63.4% mAP@50 and 46.3% mAP@50:95 on COCO, and 69.3% mAP@50 and 42.9% mAP@50:95 on Gen1. These results confirm the effectiveness of our architecture in overcoming spike-specific limitations in feature representation and fusion for object detection.

This study investigate a single-phase liquid cooling design featuring a PCB-based double H typed manifold integrated with silicon embedded microchannels, using deionized (DI) water as the working fluid, to investigate the design guideline of manifold channel depth on the thermal performances of embedded microchannel cooling. Manifolds having channel depths (dm) of 0.4 mm to 1.0 mm were fabricated in printed circuit board (PCB), which were bonded via Sn-based metallic bonding to a silicon heating area of 21 & times; 21 mm2. The thermo-hydraulic impact of the manifold channel depth was investigated through experimental characterization and numerical simulations. Our results reveal a non-monotonic dependency of cooling performance on dm, where an optimal channel depth of 0.4 mm improves cooling efficacy by intensifying jet impingement into the silicon micro-channels. The prototype demonstrates exceptional heat dissipation capacity, managing extreme thermal loads exceeding 1000 W with a low pressure drop of only 33 kPa. The system achieves an average thermal resistance of 0.21 K & sdot;cm2 & sdot;W 1 and a peak convective heat transfer coefficient of 4.75 & times; 104 W & sdot;m 2 & sdot;K 1. By transitioning the manifold layer to a PCB substrate, this design circumvents packaging complexities while maintaining compatibility with standard packaging workflows. This research provides a critical, scalable framework for the thermal management of next-generation AI and high-performance computing microsystems.

This paper presents a fully dynamic discrete-time (DT) Zoom ADC using Gain Boost floating inverter amplifiers (GBFIAs) to achieve high precision and power efficiency. The proposed GBFIA enhances the gain of a single-stage cascoded FIA to nearly 80 dB, addressing the limitation of conventional FIA in high-precision DT delta-sigma modulators. A 2-bit flash ADC with multi-input comparators is utilized for quantization noise feed-forward to mitigate fuzz in Zoom ADC. Designed and simulated in 130-nm CMOS process, the proposed Zoom ADC achieves a peak SNDR of 100.3 dB and a FoMSNDR of 181.9 dB over a 20-kHz bandwidth with oversampling rate of 128, under a 1.2-V supply. Simulations indicate the proposed Zoom ADC is power/bandwidth scalable with bandwidth ranging from 2.5 kHz to 25 kHz.

To address the bottleneck in existing readout circuits for silicon photomultiplier (SiPM) detector, where it is challenging to simultaneously achieve an ultrawide dynamic range (DR), high linearity, and sub-hundred-picosecond timing measurement, this article presents a current-mode analog front-end (AFE) chip implemented in a 130 nm CMOS process. The proposed AFE adopts a dual-path architecture: the energy path integrates a programmable-gain transimpedance amplifier, enabling linear charge measurement from single-photon events to high-dose pile-up signals up to 3600 pC, achieved through a modified regulated cascode (RGC) input stage and a current-mirror attenuation network. The timing path employs a high-speed current comparator, achieving timing jitter on the order of hundreds of picoseconds. The chip can be directly coupled to large-capacitance SiPM arrays and supports a single-channel event rate of 1.05 MHz. Measurement results demonstrate that the energy channel achieves an integral nonlinearity (INL) of less than 3.2 % over a 3600 pC input range, with a signal-to-noise ratio (SNR) exceeding 60 dB. Compared to state-of-the-art designs, this work achieves comprehensive improvements in key metrics such as DR, linearity, and event rate. This AFE provides a high-performance readout solution for SiPM detectors and can be widely applied in fields such as nuclear medicine imaging, high-energy physics, and space exploration. Future work will focus on multi-channel system verification based on a 64-channel chip.

With the miniaturization and integration of electronic devices, the power is continuously increasing, which brings a great challenge for the thermal management of the microsystems integrated with multi-chips. Particularly, in microsystem packaging, chips often have varying parameters, different sizes and heights. This variation inevitably creates gaps of differing sizes between the chips and the package cover plate in the longitudinal direction. These gaps impede efficient longitudinal heat transfer to the case. Consequently, heat accumulates within the device, negatively impacting its stability and long-term reliability. To transfer the heat to external efficiently, this study proposed a novel method to reduce the thermal resistance of the packaged microsystem, by in-situ deposition of the high thermal conductivity film on the cover plate, and then patterned to match the profile of the multi-chip section and electroplated to form cubic boss structures with different thicknesses, which fit the gaps and connect the chips with the cover plate. Hence, an efficient heat transfer path is established to reduce the junction-to-case thermal resistance substantially. A microsystem integrated with three chips was demonstrated and two substrates. SiC and diamond with corresponding boss structures were manufactured to verify the effect of the thermal transfer structure, and the results showed that using diamond for both the cover and heat transfer structure, the junction-to-case thermal resistance is less than 0.5 degrees C/W, and the maximum junction temperature of all three chips is below 78.73 degrees C under a total power of 45 W. We have established a low thermal resistance packaging structure for multi-chip microsystems. This structure provides an efficient method to transfer the heat accumulated within the microsystem to the external environment.

The complementary strengths of Spiking Neural Networks (SNNs) and Artificial Neural Networks (ANNs) have promoted interest in leveraging hybrid ANN/SNN computation. While most existing efforts focus on ANN-SNN conversion for pure SNN inference, hybrid ANN/SNN inference present unique challenges where complexity and performance in both domains are critical. Key limitations include achieving ultra-low latency, maintaining unified training parameters for resource sharing, and developing efficient neural and encoding models for hybrid data interactions. To address these challenges, We introduce the Adaptive Clip-Floor-Shift (ACFS) activation to bridge the ANN-SNN gap with unified parameters, balancing inference accuracy and complexity across both domains. Our Hybrid Neuro-Encoding Bridge (HNEB) integrating Clipped-ReLU for ANNs, proposed Selective Integrate-and-Fire (SIF) model for enhanced SNN sparsity, and a Stateless Spike Encoding (SSE) mechanism for resource-efficient activation-spike conversion. Experimental results on VGG16 and ResNet demonstrate SNNs achieving competitive accuracy ($\leq \! 0.89\%$<= 0.89% loss) versus ANNs at ultra-low latency (e.g., $T \leq 4$T <= 4 for CIFAR10, $T \leq 8$T <= 8 for CIFAR100). Experimental analysis reveals Hybrid Neural Netwroks (HNNs) provide superior energy-accuracy trade-offs, improving energy efficiency by up to 84.13% over pure SNNs while maintaining accuracy through layer-wise ANN/SNN partitioning and minimized encoding overhead.

In addressing the critical thermal management challenges posed by multi-cores and escalating power density in chiplet microsystems, this study undertakes the construction of a series of models for the interlayer microchannel structure within the 2.5D package of the chiplet microsystem. These models are devised to conduct numerical analyses of flow and heat transfer characteristics within the microchannels. Across a R number spectrum spanning from 400 to 1200, the study systematically explores the comprehensive impacts of rib filling modes and arrangements across four distinct configurations, elucidating the underlying mechanisms therein. Moreover, employing the entropy generation rate enables a thorough examination of the irreversibility associated with flow and heat transfer processes. Subsequently, the performance evaluation criterion (PEC) and the field synergy principle Fc are harnessed to compare the efficacy of various microchannel configurations. Notably, amidst the configurations under investigation, the microchannel incompletely filled with aligned ribs (MIFAR) demonstrates superior PEC performance when R numbers exceed 600. However, results derived from the field synergy principle diverge from these findings, attributable to disparities in the weighting of heat transfer capacity and flow resistance between the two criteria. These insights lay a foundation for further optimization efforts aimed at enhancing the performance and cost-effectiveness of microchannels.

Single Event Effects (SEEs) pose significant reliability challenges to deep neural networks (DNNs), particularly in aerospace environments characterized by radiation exposure. This paper introduces a comprehensive fault injection (FI) framework for systematic vulnerability assessment and mitigation of SEEs in DNN architectures. We propose a Progressive Bit Search (PBS) technique to efficiently identify sensitive layers within DNNs, combined with Triple Modular Redundancy (TMR) for hardening critical layers. Experimental results on YOLOv5 demonstrate that our approach improves fault injection evaluation efficiency by over tenfold while enhancing SEE hardening capability by more than 24 times, with a resource cost increase of less than 10%. This work addresses the critical gap between software-based FI simulations and hardware-accurate reliability assessment, providing a practical solution for radiation-hardened DNN design in aerospace applications.

The precision charge measurement of a gamma ray radiation detector consisting of scintillation crystals coupled with photomultiplier tubes (PMTs) is critical in the dark matter particle detection application. A high-resolution high-speed analog-to-digital converter (ADC) is required to digitize the amplitude of the generated pulse signals from the front-end readout electronics. In this article, we propose a novel hybrid ADC based on two-stage conversion to achieve high resolution and high sampling rate, and the key design technique of this ADC lies in optimizing the combination of successive approximation register (SAR) and time-to-digital converter (TDC) accuracy through system-level performance evaluation, ultimately achieving a high energy-efficiency ratio. A 14-bit hybrid ADC, which is composed of a 5-bit SAR, a 4-bit coarse TDC, and a 5-bit fine TDC, is proposed. A 16-channel prototype chip is designed in a 180-nm CMOS process with a 1.8/3.3 V power supply voltage. The die size is 2850 x 3350 mu m. A sampling rate of 3 MS/s is achieved at the clock frequency of 100 MHz, and the power consumption is 1.6 mW per channel. With the digital calibration, the proposed ADC achieves the differential nonlinearity (DNL) of +0.67/-0.58 LSB, the integral nonlinearity (INL) of +2.3/-0.91 LSB, the spurious free dynamic range (SFDR) of 81.59 dB, the effective number of bits (ENOB) of 11.22 bits, and the Figure of Merit (FoM) of 223.58 fJ/conv per channel.

In energy-resolved X-ray imaging, non-ideal factors impact the application-specific integrated circuits (ASICs) for pixel readout. Integrating a low-dropout (LDO) regulator within the pixel array helps to improve consistency, but the design of pixel-level LDOs faces significant challenges under stringent power, stability, and area constraints. This article proposes a novel pixel-level LDO architecture employing sub-loop (SL) compensation to simultaneously enhance stability and transient response characteristics. The SL structure generates a left-half-plane (LHP) zero to cancel the secondary pole and is driven directly by the first stage of the error amplifier (EA) without requiring additional operational amplifiers. This approach achieves a 3x reduction in compensation capacitance while maintaining a phase margin (PM) exceeding 60(degrees) across all load conditions. Furthermore, we introduce for the first time an LDO-based calibration method to mitigate the inter-pixel gain inconsistency caused by supply and ground voltage drops and manufacturing mismatches. A prototype chip has been designed and fabricated using a 130-nm CMOS process. The LDO occupies only 1500 mu m(2) of die area while consuming a quiescent current of 26 mu A. When deployed in super-pixel constructions to validate the calibration scheme, the measured standard deviations of gain variation improved from 0.25 (uncorrected) to 0.08 mV/fC (corrected).

In IoT-enabled smart infrastructure, accurate and real-time road damage detection is crucial for enhancing road safety and optimizing maintenance processes. However, detecting road damage in complex and dynamic environments presents significant challenges, such as varying lighting conditions, diverse damage types, and the need for fast processing to enable real-time decision-making. This study introduces an advanced approach utilizing the YOLOv9s-Fusion model to overcome these challenges. Leveraging the RDD2022 dataset, which comprises 1976 annotated images of road damage from China, we employ comprehensive data preprocessing to create optimal conditions for model training. The YOLOv9s-Fusion model integrates innovative features, including a Transformer-based auxiliary module and enhanced feature extraction layers, specifically designed to detect fine-grained damage patterns accurately. Experimental results demonstrate that the model outperforms existing approaches, achieving notable improvements in mean average precision (mAP) and F1-score. Ablation studies further validate the impact of our modifications, highlighting the model's robustness in real-time detection across diverse conditions. This IoT-centric approach sets a new standard for autonomous road damage detection, significantly advancing vehicle navigation and smart infrastructure management capabilities.

More advanced hybrid pixel detectors are required in the next-generation instrumentation for high-energy physics, nuclear physics, and photon science experiments. Conventional front-end readout electronics based on a pixel readout integrated circuits (ROIC) which rely on analog-to-digital converter (ADC) will encounter bottlenecks of data conversion and transmission. Deploying neural network hardware at the source end of the detector to achieve analog-to-information conversion has become an important solution to overcome these bottlenecks. In this article, we propose a novel intelligent pixel readout circuit with an all-analog in-sensor computing architecture to enable analog-to-information conversion for photon-count X-ray imaging. In this novel architecture, an analog multiplier-accumulator (MAC) unit and a ReLU circuit are integrated into a super pixel circuit to realize first-layer convolution. Then, the generated analog voltage signals are transferred to an analog in-memory computing (IMC) accelerator to complete the fully connected layer computing. A prototype with a 28 x 28 pixel matrix and an IMC macro has been designed in 180-nm CMOS technology. A binary-weight convolutional neural network (CNN) featuring 784 inputs and ten outputs is constructed. It accomplishes MNIST dataset classification task with the accuracy of 73% with an energy efficiency of 558 GOPS/W and the power consumption of 58 mu W/pixel. The area overhead and the power over head of the proposed computing circuit are only 8.3% and 8.5% of the whole application-specific integrated circuit (ASIC), respectively. The achieved results show that the integration of the pixel front-ends with in situ analog computing is highly feasible.

This paper presents a novel pixel circuit topology with a built-in pixelated low-dropout (LDO) regulator to enhance consistency in an energy-resolving photon-count pixel readout ASIC. A super pixel is organized by a 2 × 2 pixel array. A common LDO is built into the super pixel to provide a stable supply voltage for analog blocks of four pixels, ensuring the consistency of the supply voltage of each pixel unit. The maximum simulated IR drop is only 70 μV. The input charge is 1 fC ~ 10 fC. The equivalent noise charge is 200 e- (@ 200 fF). The power consumption is about 40 μW/pixel. The simulated results indicate that the proposed scheme can well enhance the consistency of the output data from each pixel readout circuit.

Road damage detection (RDD) through computer vision and deep learning techniques can ensure the safety of vehicles and humans on the roads. Integrating unmanned aerial vehicles (UAVs) in RDD and infrastructure evaluation (IE) has also emerged as a key enabler, contributing significantly to data acquisition and real-time monitoring of road damages such as potholes, cracks, and surface anomalies, facilitating proactive maintenance and improved road conditions. These UAVs are low-powered and resource-constrained devices that work autonomously to perform pattern detection and decision-making leveraging tiny machine learning (Tiny ML) algorithms. These Tiny ML algorithms are designed to run on edge devices, IoT devices, UAVs, etc. In this study, the RDD2022 dataset collected using UAVs and dashboard cameras of vehicles was utilized to train pure and mixed models that exhibit class instance imbalance in certain classes which is addressed by implementing data augmentation as a regularization technique. State-of-the-art two-stage detectors; Faster R-CNN ResNet101 and one-stage detectors; SSD MobileNet V1 FPN, YOLOv5, and Efficientdet D1 are employed. The results indicate that the two-stage detector achieved an impressive mAP of 88.49% overall and 96.62% for focused classes. Notably, the state-of-the-art Efficientdet D1 approach achieved a competitive mAP of 86.47% overall and 95.12% for focused classes, with significantly lower computational cost. These findings highlight the potential of advanced object detection techniques, particularly Efficientdet D1, to enhance the accuracy and efficiency of RDD systems, thereby improving passenger safety and overall performance.

The identification of road damage is deemed very important to the preservation of infrastructure. Since recent development in deep learning provide great potential approaches, in this paper, three deep learning models, namely EfficientNet, CNN and YOLOv8 are considered and their performance is evaluated on a dataset with 8,586 images with labelled road damages consisting of seven subclasses including longitudinal cracks and potholes. Besides, other issues like class imbalance and variabilities in the environment were studied and considered in its assessment based on the Models accuracy, precision, recall, and F1-score. With an accuracy of 64%, YOLOv8 is the most accurate model for identifying various types of damages, particularly in identifying multiple damages present in one or more types of damage, as was seen in the high accuracy rate of a split sample of 44 images of multiple damages. Our findings showcase YOLOv8 as a strong contender for real-time road damage detection with potential of enhancement with better augmentation and fine-tuning.

A portable electronic personal dosimeter (EPD) with a battery supply is widely used to monitor the dose equivalence of staff in nuclear radiation environments, requiring both a low energy detection limitation and a long operation period. Recently, a commercial silicon p-i-n (Si-PIN) detector has been proposed as a radiation sensor due to its advantages of low cost and high sensitivity. However, such a detector suffers from a large parasitic capacitance, i.e., 20 pF at a supply of several tens of volts. Thus, designing a low-noise front-end readout application-specific integrated circuit (ASIC) at low power dissipation is very critical. In this article, we propose design techniques and characterization of a fully customized low-noise ASIC for this application. An improved charge-sensitive amplifier (CSA) and a CR-(RC)(3) pulse shaper with programmable shaping time are proposed to achieve both a low noise floor and a smaller slope of equivalent noise charge (ENC) at room temperature. A four-channel ASIC has been successfully developed in the 0.35 mu m complementary metal oxide semiconductor (CMOS) process. The die size of the prototype chip is 2.5 x 2.5 mm. The dynamic range of input charges is 0.2-15 fC. The ENC is 102 + 3.5 e(-) (rms) per picofarad under a power dissipation of similar to 2 mW/channel. Through the measurement of the ASIC connected to a Si-PIN detector, the energy resolution is 3.8% full-width half maximum (FWHM) at the 59.5 keV of the radioactive source 241 Am. The energy detection threshold is less than 5 keV and the maximum count rate is 320 kcps. The proposed ASIC has passed the verification of a stereotyped EPD.

The ability to support multitasking becomes more and more important in the development of graphic processing unit (GPU). GPU multitasking methods are classified into three types: temporal multitasking, spatial multitasking, and simultaneous multitasking (SMK). This article first introduces the features of some commercial GPU architectures to support multitasking and the common metrics used for evaluating the performance of GPU multitasking methods, and then reviews the GPU multitasking methods supported by hardware architecture (i.e., hardware GPU multitasking methods). The main problems of each type of hardware GPU multitasking methods to be solved are illustrated. Meanwhile, the key idea of each previous hardware GPU multitasking method is introduced. In addition, the characteristics of hardware GPU multitasking methods belonging to the same type are compared. This article also gives some valuable suggestions for the future research. An enhanced GPU simulator is needed to bridge the gap between academia and industry. In addition, it is promising to expand the research space with machine learning technologies, advanced GPU architectural innovations, 3D stacked memory, etc. Because most previous GPU multitasking methods are based on NVIDIA GPUs, this article focuses on NVIDIA GPU architecture, and uses NVIDIA's terminology. To our knowledge, this article is the first survey about hardware GPU multitasking methods. We believe that our survey can help the readers gain insights into the research field of hardware GPU multitasking methods.

Image stitching plays an important role in the field of computer vision and image processing. Although some sophisticated stitching methods have been proposed, they are usually time-consuming. Because many application scenarios, such as video surveillance, need quick image stitching to provide a wide field of view, accelerating the image stitching is critical. In recent years, the neural network is used to stitching images, but only relatively small size images can be processed; meanwhile, time-consuming image stitching is also unavoidable. In this paper, to quickly stitch 1920×1080 images generated by the dual camera system, an image stitching algorithm is proposed. We divided the algorithm depending on its timeliness on different steps, and its time-consuming steps are parallelized on Graphics Processing Unit (GPU) platforms to be accelerated. We tested different hierarchies for organization of threads and access of memory on compute unified device architecture (CUDA) programming, and the final experiment results showed that our algorithm could reach a speedup ratio up to 119x on the Desktop with 3080ti.

The application of hybrid pixel detectors with a dynamically selectable readout mode in X-ray imaging is highly desirable. The concept of a detector system that can switch readout mode under different conditions is demanded to realize fast and versatile imaging. This paper presents design techniques and preliminary results of a pixel readout ASIC prototype with a reconfigurable readout scheme in a 180 nm CMOS process for silicon pixel detectors. A bus-based reconfigurable data readout scheme is presented. Three readout modes are realized: full-frame readout, zero-suppression readout, and region-of-interest readout. In particular application scenarios, the readout mode will be switched based on the number of pixels with valid data to improve the frame rate. Assuming that all pixels with valid data are transmitted, the reconfigurable data readout method saves 40 % of the data transmission time than zero-suppression readout under 50 MHz.