ABSTRACT The multifunctional integration of chips with high flexibility and scalable manufacturing is crucial for enhancing chip performance, reducing chip size, and simplifying chip design. However, balancing volume, cost, flexibility, and functionality using traditional heterogeneous integration methods is challenging. To overcome this, a silicon‐embedded multifunctional heterogeneous integration method based on top‐down engineering was proposed. As a representative application, a wearable photoplethysmography detection system was demonstrated. The functional modules of this system required for sensing, acquisition, and processing were embedded and reconnected on the same silicon interposer to form a new integrated chip. A thermal‐aware floorplan optimization algorithm was employed to improve the thermal performance of the integrated chip, achieving a 6.5°C reduction in the peak temperature. The chip accurately detected physiological changes across different frequency ranges following physical activity performed at varying intensities by test participants. Compared to traditional integration methods, the proposed method achieved a 46% and 94.7% reduction in power consumption and volume, respectively, and a remarkable 90% increase in functional unit density. This technology promotes rapid, flexible, and low‐cost manufacturing of multifunctional chips toward the development of next‐generation multifunctional, low‐power, miniaturized electronic devices.

Silicon-based manifold microchannel heat sinks (MMHSs) have demonstrated strong heat dissipation capability but show clear performance limitations under extreme heat fluxes. Diamond, with its exceptional thermal conductivity, offers a promising pathway toward managing ultra-high heat fluxes. However, studies on diamondbased MMHSs that integrate manifold architectures for efficient fluid delivery remain relatively limited. Here, we present a fully diamond-based embedded manifold microchannel heat sink (FDMMHS) for ultra-high heat flux thermal management. Two configurations with channel widths of 100 mu m and 50 mu m were fabricated and tested using heat sources of 1 mm x 1 mm and 3.4 mm x 3.3 mm, respectively. The 1 mm x 1 mm hotspot sustained a record high heat flux of 10,000 W center dot cm-2 with a temperature rise of 120 K, while the larger 3.4 mm x 3.3 mm heat source handled 1000 W center dot cm-2 with only a 42 K temperature rise. The corresponding effective convective heat transfer coefficients reached 1.3 x 105 W center dot m-2 center dot K-1 (50 mu m channels, large heat source) and 3.5 x 104 W center dot m-2 center dot K-1 (100 mu m channels, small heat source), among the highest values reported for single-phase microfluidic cooling. These results highlight the synergistic advantages of diamond's superior thermal conductivity and manifoldbased flow routing architectures. The FDMMHS demonstrates good potential for compact electronic systems requiring reliable heat management. It also provides a foundation for further optimization through advanced diamond microfabrication.

The ability to map protein identity, with resolution sufficient to infer interactions, would support analysis of how proteins work together, or malfunction, in biological processes and diseases. Although several emerging technologies aim towards single-molecule protein sequencing, they require proteins to be removed from the nanoscale spatial context of cells and tissues. Expansion microscopy (ExM) has facilitated a diversity of chemical analyses by isotropically separating molecules throughout a specimen after permeation via a charged hydrogel, followed by gel swelling. Here, we adapt key protein sequencing steps - Edman degradation and amino acid recognition - to the ExM gel context. Using testbed peptides in ExM gels, we show that N-terminal amino acids can be recognized over multiple cycles of in-gel Edman degradation. These results establish principles of in situ protein sequencing and provide a framework for future in situ protein sequencing developments, including the development of higher specificity and affinity amino acid binders.

This study investigate a single-phase liquid cooling design featuring a PCB-based double H typed manifold integrated with silicon embedded microchannels, using deionized (DI) water as the working fluid, to investigate the design guideline of manifold channel depth on the thermal performances of embedded microchannel cooling. Manifolds having channel depths (dm) of 0.4 mm to 1.0 mm were fabricated in printed circuit board (PCB), which were bonded via Sn-based metallic bonding to a silicon heating area of 21 & times; 21 mm2. The thermo-hydraulic impact of the manifold channel depth was investigated through experimental characterization and numerical simulations. Our results reveal a non-monotonic dependency of cooling performance on dm, where an optimal channel depth of 0.4 mm improves cooling efficacy by intensifying jet impingement into the silicon micro-channels. The prototype demonstrates exceptional heat dissipation capacity, managing extreme thermal loads exceeding 1000 W with a low pressure drop of only 33 kPa. The system achieves an average thermal resistance of 0.21 K & sdot;cm2 & sdot;W 1 and a peak convective heat transfer coefficient of 4.75 & times; 104 W & sdot;m 2 & sdot;K 1. By transitioning the manifold layer to a PCB substrate, this design circumvents packaging complexities while maintaining compatibility with standard packaging workflows. This research provides a critical, scalable framework for the thermal management of next-generation AI and high-performance computing microsystems.

Two-phase jet impingement cooling is a promising technique for heat dissipation of high-power electronics, offering high heat transfer coefficients by directly targeting coolant onto hot surfaces. In this study, we propose copper inverse opal coated microfins (CCMs) for enhanced two-phase jet impingement cooling. A dielectric fluid (Novec 649) is used as the coolant to ensure electrical insulation. Experiments are conducted on a chip-level jet impingement setup at a fixed 20 degrees C inlet temperature, across varying flow rates (1.5-3.5 L/min) and heating powers. The test section integrates a distributed slot-jet polyamide manifold with peripheral outlets for vapor and excess-liquid discharge, enabling uniform liquid delivery and stable two-phase operation. Boiling curves, thermal resistances, and on-chip temperature uniformities are obtained for multiple CCM samples having different pore sizes, neck diameters, and thicknesses of the copper inverse opal (CIO) layer. Due to abundant nucleation sites and capillary wicking provided by the CIO layer, the CCM surface having CIO pore diameter of 1 mu m and thickness of 20 mu m achieves critical heat flux (CHF) of 181 W/cm2 at a 19 K superheat. The temperature difference across the 3.36 cm2 heated area at 552 W power input is around 10 K, indicating excellent temperature uniformity. This work highlights the efficacy of CCM surfaces in two-phase jet impingement cooling with Novec 649, paving the way for safe and efficient thermal management of electronics using dielectric fluids.

Polymer-based embedded silicon-based fan-out (P-eSiFO) is a new packaging technique, which provides a way to high-density integration of high-performance chiplets. However, integrating multiple materials with diverse physical properties in the P-eSiFO leads to substantial warpage during downstream high-temperature manufacturing processes. In this study, a thermomechanical model of a P-eSiFO was developed to examine the thermomechanical with varying structural parameters and material selections. Test dies having an area of 0.5 cm(2) were embedded in a 500-mu m-thick silicon carrier following the P-eSiFO process. After careful parameters, optimization chip warpage can effectively decrease by over 60%. Experimental results showed that the height difference between the embedded chip and its silicon interposer can be reduced down to 1 mu m with optimized parameters after high-temperature processes. This work provides useful insights for addressing multimaterial warpage concerns during thermal processes in advanced packaging.

Lipid membranes are key to the nanoscale compartmentalization of biological systems, but fluorescent visualization of them in intact tissues, with nanoscale precision, is challenging to do with high labeling density. Here, we report ultrastructural membrane expansion microscopy (umExM), which combines an innovative membrane label and optimized expansion microscopy protocol, to support dense labeling of membranes in tissues for nanoscale visualization. We validate the high signal-to-background ratio, and uniformity and continuity, of umExM membrane labeling in brain slices, which supports the imaging of membranes and proteins at a resolution of ~60 nm on a confocal microscope. We demonstrate the utility of umExM for the segmentation and tracing of neuronal processes, such as axons, in mouse brain tissue. Combining umExM with optical fluctuation imaging, or iterating the expansion process, yields ~35 nm resolution imaging, pointing towards the potential for electron microscopy resolution visualization of brain membranes on ordinary light microscopes.

High-density packaging of MEMS-IC is essential for enabling high-performance integrated systems. This paper presents a novel packaging fabrication technique for MEMS sensors and ICs. The MEMS photoelectric sensors and IC amplifiers were integrated within a silicon interposer with the feature size of the electrical interconnections reduced to 2 mu m leveraged by photolithography process and die-shift is less than 3 mu m through optimized microfabrication. Additionally, the prepared photoelectric microsystems realized excellent photoelectric response effects. This packaging technique is fully compatible with MEMS microfabrication processes, enabling heterogeneous integration with miniaturized interconnections and high fabrication yield. This fabrication strategy shows great promise for realizing heterogeneous and size-varied device integration for advanced MEMS-based microsystems.

Reconfigurable antennas have attracted significant interest because of their ability to dynamically adjust radiation properties, such as operating frequencies, thereby managing the congested frequency spectrum efficiently and minimizing crosstalk. However, existing approaches utilizing switches or advanced materials are limited by their discrete tunability, high static power consumption, or material degradation for long-term usage. In this study, we present a W-band frequency reconfigurable antenna that undergoes a geometric transformation from a two-dimensional (2D) precursor, selectively bonded to a prestretched elastomeric substrate, into a desired 3D layout through controlled compressive buckling. Modeling the buckling process using combined mechanics-electromagnetic finite element analysis (FEA) allows for the rational design of the antenna with desired strains applied to the substrate. By releasing the substrate at varying compression ratios, the antenna reshapes into different 3D configurations, enabling continuous frequency reconfigurability. Simulation and experimental results demonstrate that the antenna’s resonant frequency can be tuned from 77 GHz in its 2D state to 94 GHz in its 3D state in a folded-dipole-like design.

This study presents a compact and low-loss receiver module for Ka-band applications, featuring the first integration of an antenna and a low-noise amplifier (LNA) using an embedded glass fan-out packaging method. The design achieves a low package loss of 0.5 dB by employing metal planarization to reduce transmission line roughness, utilizing a glass substrate with low dielectric constant (Dk) and low loss tangent (Df), and implementing ultra-short redistribution layer (RDL) interconnects. Additionally, a customized die-to-antenna impedance matching network expands the bandwidth by 57% compared to a 2.92 mm SMA connector. Unlike prior studies using dummy dies, this work demonstrates a fully functional, packaged, and measured LNA die, providing practical validation of performance.

Embedded Silicon Fan-out (eSiFO) packaging is considered one of the ideal advanced packaging technologies due to its suitability for heterogeneous integration and its exceptional electrothermal performance. This study employed the H-eSiFO process to package a CMOS operational amplifier chip, analyzing the impact of various packaging process steps such as chip thinning and dicing, surface passivation, and the fabrication of the redistribution layer on chip performance. A corresponding test circuit was designed for the packaged chip to conduct functional performance tests. The results indicate that this packaging method does not adversely affect the chip's performance, demonstrating the potential of H-eSiFO in the advanced packaging of Chiplet.

The removal of high heat fluxes is an important problem for electronics in applications including high frequency amplifier, electric vehicles, and high-performance computing. This research aims to optimize the geometric parameters of the metal fins embedded with PCM for the transient heat dissipation requirements of high power density electronics. A comparison was carried out between heat sink with and without phase change material (PCM). The effects of various parameters such as number of fins, fin thickness, fin heigh, fin length and power levels were studied. Simulations show that increasing the number of fins can significantly improve the cooling performance. However, when the number of fins reaches a critical value, the heat dissipation performance does not improve more. Furthermore, different numbers of fins have their respective optimal fin thicknesses. Through finite element simulation analysis, the optimized fin embedded with PCM heat sink reduces the maximum temperature of the heat source to 159°C. This signifies a 64% decrease compared to a pure PCM heat sink, and a 47% decrease compared to a pure metal heat sink. Additionally, the study found that increasing the fin length and height effectively reduces the heat source temperature. The optimal fin thickness increases to accommodate the higher heat flux encountered during transient heat transfer processes.

Driven by the demands of the intelligent industry, the thermal management of high power chips is causing huge concern. In the last several decades, microfluidic cooling has demonstrated great potential in device cooling applications. This paper presents a monolithically integrated manifold microchannel cold plate that can become a general embedded cooling method for most chips. The test samples are fabricated by the MEMS process and test. The experimental result shows that the cold plate can remove more than 500W/cm 2 heat with a thermal resistance below 0.25 K•cm 2 /W and the global average convective heat transfer coefficient was approximately 43300 W/m 2 •K. This approach is important for solving thermal management challenges in electronic devices.

Controlling warpage is of key importance for realizing reliable and cost-efficient advanced packaging. However, warpage effects can occur during the manufacturing process, caused by a combination of different processing temperatures, different materials, and the changing properties of the materials (e.g. polymerization and related cure shrinkage). One approach to controlling warpage could be realized by assessing a numerical simulation workflow of the advanced packaging process chain and prefabricate back- side film, in which the relevant material properties and geometry are used as input. Polymers are easy to prepare, compatible with advanced packaging processes, and can achieve a wide range of stress transformation. In this paper, a warpage control method by prefabricating backside polymer film and a Multi-physics finite element model was proposed. The results show that the polymers can achieve wafer-level warpage control in the curvature range of 0.003 similar to 0.041 on a 4-inch Si wafer.

Driven by the wider application of the new generation of wide-bandgap materials, thermal management for high power electronic devices is becoming a growing concern. Microfluidic cooling technology is considered a promising technology to overcome the thermal challenge because it allows for more efficient heat dissipation due to the powerful heat convection of the liquid. In this paper, by employing a numerical study, a hybrid discontinuous microchannel heat sink combining manifold with pin fins (DMC-MPF) is proposed. Compared to the traditional design, the DMC-MPF enhances heat transfer and reduces flow resistance especially when the thermal conductivity of the microchannel is low. In particular, for a 2 × 2 mm 2 chip at a pressure drop of 50 kPa, the thermal resistance can reach to 0.04°C‧cm 2 /W. Compared to the original design, when the thermal conductivity of the microchannel is 2 W/m‧K and the heat flux at 1500 W/cm 2 , the DMC-MPF can reduce the maximum temperature by 50 % and improve the temperature uniformity significantly. This work provides a very promising and efficient single-phase microchannel cooling scheme used in the thermal management of RF electronics with high heat flux.

As Moore’s Law tends to reach its limits, shrinking process technology nodes is no longer the most effective way to improve the performance of systems, and more attention is being focused on advanced packaging. Thermal dissipation as the main issue severely limits the reliability of 3D stacked modules. Embedded cooling is a feasible solution for interlayer cooling. However, the current manifold is incompatible with advanced packaging processes due to the footprint and manufacturing process. In this work, a manifold microfluidic cooling structure for embedded silicon Fan-Out (MMC-eSiFO) package is proposed and the thermal test vehicle (TTV) is designed, fabricated and tested. A silicon-based interposer is formed using a wafer bonding process by etching a cavity structure and a manifold channel on two silicon wafers, respectively. The large-area high-power chip is embedded into the cavity for effective cooling by the embedded microchannels. A high-density redistribution layer (RDL) is used to fan out the electrical I/O after fabricating the dielectric layer on the surface. In addition, multi-layer embedded liquid cooling of 3D package structure can be achieved by interposer with through silicon vias (TSVs). The use of a silicon-based interposer not only enables high aspect ratio TSVs and high-density RDL but also helps to reduce thermal stress in the package structure, as the interposer material is the same as the IC chip material. It is worth noting that the fabrication of the interposer and fan-out layer is wafer-level processing that enables production at scale. Multiple sets of cavities and manifold channels can be etched in a single package structure, making it compatible with chiplet technology. The package structure is expected to solve the thermal dissipation problem of multi-layer multi-chip assemblies.

Evaporation from nanopores is of great interest in nature and many industrial applications. Therefore, understanding the transport processes within a pore requires integrating the dynamics of vapor and liquid flow, and interfacial interactions are essential. The vapor movement is classified as free molecular flow due to the modest size of the pore (about 100 nm) compared to the mean free path (roughly 1.1 mu m). Our research will begin by determining the possibility of liquid molecules evaporating from the surface and entering the pore and the probability of vapor molecules condensing back onto the surface once they reach the pore's end. We then investigate the effects of various operating factors to identify settings that optimize nanopore evaporation.

Embedded silicon fan-out packaging (eSiFO) features excellent electrical and thermal performances as well as scalability to 3-D packaging and heterogeneous integration, making it a promising packaging technology for chiplet integration. Nevertheless, conventional eSiFO implementation resorts to a dry film vacuum lamination process for surface passivation of reconstituted wafers, which is challenged by low lithographic resolution, limited compatibility, difficulty in filling high-aspect trenches, and elevated costs due to the inherent attributes of dry film materials. This work proposes a new surface passivation method of eSiFO, which uses Parylene to fill trenches and polyimide (PI) to passivate the reconstructed wafer surface. The trench with an aspect ratio greater than 10 and a width less than $5 ~\mu \text{m}$ can be filled successfully. The height difference of the reconstructed wafer surface after polymer passivation was less than $1 ~\mu \text{m}$ . Finally, three different wiring methods were proposed to implement two-layer high-density damascene wiring (linewidth/line space $ < 2 /2 ~\mu \text{m}$ ). This approach is characterized by its ease of implementation, cost-effectiveness, superior compatibility, high chip area efficiency, minimized die shift, and capability to facilitate high-density redistribution layer (RDL) wiring. Given these attributes, this approach indicates a propitious future for advanced packaging techniques of chiplet.

Hydrogels are extensively used as tunable, biomimetic three-dimensional cell culture matrices, but optically deep, high-resolution images are often difficult to obtain, limiting nanoscale quantification of cell–matrix interactions and outside-in signalling. Here we present photopolymerized hydrogels for expansion microscopy that enable optical clearance and tunable ×4.6–6.7 homogeneous expansion of not only monolayer cell cultures and tissue sections, but cells embedded within hydrogels. The photopolymerized hydrogels for expansion microscopy formulation relies on a rapid photoinitiated thiol/acrylate mixed-mode polymerization that is not inhibited by oxygen and decouples monomer diffusion from polymerization, which is particularly beneficial when expanding cells embedded within hydrogels. Using this technology, we visualize human mesenchymal stem cells and their interactions with nascently deposited proteins at <120 nm resolution when cultured in proteolytically degradable synthetic polyethylene glycol hydrogels. Results support the notion that focal adhesion maturation requires cellular fibronectin deposition; nuclear deformation precedes cellular spreading; and human mesenchymal stem cells display cell-surface metalloproteinases for matrix remodelling.