By using Silvaco-TCAD simulation software, the influences of the emitter surface concentration (cE), the junction depth (xj) and the emitter fraction (EF) on the output characteristics of P-type front junction back contact crystalline silicon solar cell was analyzed. The results show that the upper surface emitter surface concentration and the junction depth of the front junction back contact crystalline silicon solar cell based on conventional low-cost P-type silicon substrate (CZ growth method, the resistivity is 1.5Ω·cm, the minority carrier life is 10μs) have a noticeable effect on output characteristics of solar cells. The higher the upper surface emitter surface concentration, the deeper the junction depth, the lower the short wavelength incident light external quantum efficiency. When the upper surface emitter surface concentration is 1×1019 cm–3 and the junction depth is 0.2μm,the solar cell conversion efficiency reaches 20.72%. The side-surface and under-surface emitter surface concentration and the junction depth have a slight effect on output characteristics of solar cells, while the side-surface and under-surface emitter fraction has a noticeable effect on output characteristics of solar cells. The greater the side-surface and under-surface emitter fraction, the higher the external quantum efficiency and conversion efficiency.

In 2010, Shiu et al. proposed three DNA-based reversible data hiding schemes with high embedding capacity. However, their schemes were not focused on DNA modification rate or the expansion problem. Therefore, we propose a novel reversible data hiding scheme based on histogram technique to solve the weaknesses of Shiu et al.'s schemes. The proposed scheme transforms the DNA sequence into a binary string and then combines several bits into a decimal integer. These decimal integers are used to generate a histogram. Afterwards, the proposed scheme uses a histogram technique to embed secret data. The experimental results show that the modification rate of our proposed scheme is 69 % lower than that of Shiu et al.'s schemes for the same embedding capacity. In addition, the length of the DNA sequence remains unchanged in the proposed scheme.

A low dropout linear regulator (LDO) circuit without off-chip capacitor is designed for 3.3 V and maximum 100 mA output. The LDO's transient characteristic is improved by using parallel-connected differentiators. The stability of the system is enhanced due to Miller compensation which eliminates the large output voltage ripple of the capacitor-free LDO. The circuit is designed by means of 0.5 µm technological process. The Cadence Spectre simulation results show that the quiescent current consumption of the circuit is 25 µA under 3.5 V supply voltage, the phase margin is 70° without load, the ripple of output voltage is less than 200 mV with the load current changing from 0 to 100 mA in 1 µs.

Using the Taguchi method, the authors analyzed the optimum conditions for (Y3−xCex)Al5O12 (YAG:Ce) phosphor, which is prepared using the solid-state reaction method. The controllable factors used in this study consisted of the following: (1) the duration of milling, (2) the quantity of substitution, (3) the duration of sintering, and (4) the temperature of sintering. Under optimum conditions, a confirmation experiment was carried out, and the average photoluminescence (PL) intensity of YAG:Ce phosphor was found to be up to 270.84 (a.u.). The percentage contribution of each controllable factor was also determined. Most interestingly, the temperature of sintering is the most influential factor within current investigation range to the solid-state-prepared YAG:Ce phosphor, and its value of percentage contribution is up to 70.90%. Aside from this, through the optimum conditions, the average PL intensity of YAG:Ce phosphor can be substantially promoted from 193.88 (a.u.), the average PL intensity of YAG:Ce phosphor sintered at 1500°C for 6h that was usually used to sinter YAG:Ce phosphor.

A low mismatch Curvature-Compensated CMOS bandgap reference by the mechanism of chopper modulator,we use a first-order folding amplifier,which has a simple structure,low power consumption and smaller layout area than second-order,it still has a good gain.We use second-order current compensation,make the BGR a better temperature coefficient and the system is stable.We use a standard 0.5μm CMOS process to simulate the op-amp circuit and bandgap reference circuit.The circuit delivers an output voltage of 1.17V,and achieves temperature coefficient of 4.7 ppm over-20 ℃ to 120 ℃ We can choose a different process and passive resistance to make the different reference voltage,temperature coefficient is still enough to meet the actual needs.

To prevent overheating of the chip and improve the reliability and stability of the chip,using a 0.5 μm CMOS process,a thermal shutdown circuit with hysteresis comparator was designed.The structure of the folded cascade OPA was used in the comparator,so the comparator had a large input range as well as better hysteresis performance and temperature sensitivity.The circuits ware simulated by the cadence spectre,the results show that when the supply voltage is in the range of 4.5-7 V,the threshold voltage of over-temperature protection changes in a small amount,which means that the output signal has a good power supply rejection.When the temperature exceeds 130 ℃,the output signal turns over and the ship stops working.When the temperature falls down to 90 ℃,the chip works again.This circuit can control the magnitude of two threshold voltages by adjusting size of specific transistor,and because of this special function it avoids the thermal swing.

This study investigates effects of the zinc oxide (ZnO) addition and the sintering temperature on the microstructure and the electrical properties (such as dielectric constant and loss tangent) of the lead-free piezoelectric ceramic of bismuth sodium titanate (Na0.5Bi0.5TiO3), NBT, which was prepared using the mixed oxide method. Three kinds of starting powders (such as Bi2O3, Na2CO3 and TiO2) were mixed and calcined. This calcined NBT powder and a certain weight percentage of ZnO were mixed and compressed into a green compact of NBT–ZnO. Then, this green compact of NBT–ZnO was sintered to be a disk doped with ZnO, and its characteristics were measured. In this study, the calcining temperature was 800°C, the sintering temperatures ranged from 1000 to 1150°C, and the weight percentages of ZnO doping included 0.0, 0.5, 1.0, and 2.0wt%. At a fixed wt% ZnO, the grain size increases with increase in the sintering temperature. The largest relative density of the NBT disk obtained in this study is 98.3% at the calcining temperature of 800°C, the sintering temperature of 1050°C, and 0.5wt% ZnO addition. Its corresponding dielectric constant and loss tangent are 216.55 and 0.133, respectively.

A PLL used for stereo demodulation in FM broadcasting was designed in 1.5 μm bipolar process.Compared with traditional Gilbert cell,the structure of the phase detector was changed into upper and lower symmetrical dual-switch circuit.Its sensitivity and phase-detect range were increased.A DC amplifier was added in the loop.By adjusting the gain of the amplifier,a trade-off between the loop's steady state,lock time and noise bandwidth was get.The circuit of the crystal VCO in the loop with a high-Q crystal that used for the resonator network of the VCO was designed.It can get a high Q value of the narrow-band phase-locked loop,and can reduce the VCO phase noise.

A mode for designing the digital logic circuit through C ++ language matching withVerilog HDL was introduced. Base on this,a brand-new method of designing logic circuit from C ++ toVerilog was presented. This method starts from the system design ( virtual machine) and used C ++ tobuild the required system model. Then,the software design is accurately translated into a hardware levelby Verilog and C ++ consistency. So the logical design upwards can undertake joint simulation by software and hardware,and downwards can realize physical level outspread. This method can effectively avoid logic inconsistency when the SOC design is translated from system design to physical design. Some contrastive analyses about the difference of two languages were given after some language characteristics of C ++ were formulated. Then translation way was given between C ++ and Verilog HDL. Besides,the example of DSP designing was provided which can perform application of this method directly. Finally,the system description was verified by comparing the simulation data of C ++ and Verilog.

This paper describes a design and implementation of SPI interface model which is used for a SoC chip. The objective of this design is to realize expediently communicate between SoC chip and peripheral equipment. The paper analyses the sequence of SPI protocol, describes the design project of implement SPI logical function. Besides, the design is compatible with the SPI protocal and the function is also expanded, finally achieves powerful in function. After testbench and FPGA verification, the SoC chip that used this SPI model had been successfully processed. The test results indicate that the SPI interface controller's function and performance are all achieve design target, many communication tests indicate the design is reliable in performance.

The article analyzed the domestic and international CRC checking methods which are applied to Smart Card, and deep research on Smart Card standard and the CRC polynomial. On this basis, the two types of CRC calculation are mixed together, and a new hardware realization method is presented combining with Smart Card standard. According to this method a hardware design of CRC calculation module is completed. The design had been simulated on RTL level, verified by the FPGA, and successfully processed. The chip has passed flow pieces tested. The results showed that the module function and performance reached design target, the performance is good.

In SOC design,digital design are increasingly sophisticated;having multiple clocks driving different circuits and circuits that must reliably communicate with each other.This paper explores the fundamentals of signal synchronization and demonstrates circuits a designer can used to handle signals that cross clock domains.It examines design methodologies include handshake and FIFO design for synchronizing groups of signals including data busses that cross clock domains.

In this article,a design method of low power Gm_OTA which contains bandgap reference,the construction and neaten of circuit are finished in schematic of Candence,and the basic struction is analyzed.Basis on that,the system model is also established by Hspice Tool.At the same time,the simulation of the system model are accomplished through.Under 7.75V,on the basis of csmc 0.5um technics model,75pF load is drived by the design,the phasic margin is 135 degree,the unit plus bandwidth is 1.19MHz,the static power is 3.43mW,and good capability of low power Gm_OTA is carried out.

In the traditional IP verification methodology, module level verification platform have limitations such as uncontrollability, low efficiency, huge workload, long verification time and poor reusability. To resolve these problems, a SOC function verification virtual platform based on bus transaction level strategy is proposed. The virtual verification platform is composed of system component function models, which are described by high level abstraction modeling methods. The platform provides incentives in bus transaction mode based on simulation. The experimental results of practical application show that the platform can improve IP verification efficiency and enhance IP verification reusability. The practical construction and methodology can be used in other function verification platform.

Direct current glow discharge has been employed to prepare the SIPOS passivation films on the beveled power semiconductor devices.Results obtained indicates that the performance of power semiconductor devices passivated by SIPOS are improved,and SIPOS based process is effective and expected to enhance the reliability of device.Based on this,the SIPOS/PI passivation structure is proposed to improve the characteristic of the surface of beveled power semiconductor device.

文章阐述了∑-△调制器的基本工作原理,构建了二阶∑-△调制器的基本结构,提出了一种用verilog HDL语言描述二阶∑-△调制器的实现方法,其中采用了简单的移位方法来描述调制器的四个增益系数,以实现乘法操作,进而减小了芯片的面积.在此基础上,运用MATLAB系统工具建立了二阶∑-△调制器系统的模型,并完成了系统仿真验证.在电路级完成了它的Verilog语言描述,同时运用modelsim仿真工具对电路进行仿真验证,对数据进行FFT分析,最终证明了MATLAB系统模型和Verilog代码的一致性.

This paper proposes a reversible data-embedding scheme that improves on Kieu and Chang's method by increasing the embedding capacity measured by bits per pixel (bpp) while maintaining high image quality. The embedding procedure of the proposed method consists of two phases: "horizontal embedding" and "vertical embedding." Every overlapping pixel pair can carry one secret bit for enhancing the embedding capacity. The experimental results show that the PSNR value of one-layer embedding is greater than 52 dB, and the embedding capacity is more than 1 bpp for all 512x512 test images. Even after four-layer embedding, the experimental results show that the embedding capacity of test images is more than 4.8 bpp and the PSNR value is higher than 51 dB. The results show that the proposed method has superior measures in both image quality and embedding capacity.

文章采用自上而下(TOP-D0WN)分析方法,对单环结构的四阶∑-△调制器进行了系统设计与仿真,电路设计与仿真.在系统级提出了基于systemview的高层次建模,通过系统仿真确定了关键的电路参数和性能指标.并采用前馈的方法避免了运算放大器的非线性造成调制器失真.在电路结构级采用了全差分形式,利用开关电容电路.再配合互不重叠时钟的控制,构造出系统所需的开关电容积分器.并且采用截断(chopping)技术,减小实际电路中的闪烁噪声.