With the rapid development of Internet technology, information security has become increasingly important. Cryptographic analysis techniques, especially side-channel analysis (SCA), pose a significant threat to security systems. The latest SCA technology mainly utilizes the physical leakage signals generated during the operation of encryption devices, such as power consumption, temperature and electromagnetic radiation. These signals themselves carry the physical characteristics of the device, which are related to the encryption algorithm. Among them, the power consumption trace remains the main target of modern SCA research. However, such trajectories often bring about some analytical difficulties, such as the data sequence being too long, the feature points being distributed sparsely, and the internal relationships of the data being complex. These challenges hinder effective analysis. While Transformer architectures are good at capturing long-range dependencies in sequential data, their high computational complexity limits practical deployment. To address this, we propose replacing the self-attention (SA) module in Transformers with a focal modulation module. This modification significantly reduces computational complexity and reduces computational operations during feature extraction, enabling efficient and accurate side-channel attacks. Experimental results on benchmark datasets (ASCAD, AES_RD, AES_HD, DPAv4) demonstrate the superiority of our approach. The proposed method achieves a reduction in training time compared to standard Transformer models, and achieves superior key recovery performance, outperforming existing state-of-the-art models.

This paper proposes SCABoosting, a novel boosting framework for deep learning-based Side-Channel Analysis (SCA) that significantly enhances key recovery efficiency while maintaining computational lightweightness. Our method integrates multiple randomly generated CNN classifiers through a sequential boosting strategy, achieving superior performance with only 26 M parameters compared to 68 M parameters required by state-of-the-art CNNbest models. Extensive evaluation on three standard datasets demonstrates compelling results: on ASCAD dataset, our approach reduces guessing entropy (GE) to 102 (vs 204 for CNNbest) and achieves 92

The explosive growth of micro-satellites has brought about increasingly saturated competition for low Earth orbit resources, and more complex potential needs of on orbit operations grow quickly. Aerospace robotic arms are still the most important optimal option to replace human beings to perform complex operation tasks for a long term. Faced with extreme requirements and environmental constraints different with on the ground, the miniaturization of the electronic system is the bottleneck that determines space robots' performance and energy efficiency ratio. This paper proposes an architecture of reconfigurable integrated processing microsystem for the application of micro space dual arm robotics. The core architecture design is studied from the task demand orientation, with processing, communication, sensing, execution, control and other functions in a highly integrated architecture, through system modeling, simulation and software hardware collaborative design. A corresponding assessment is provided for the subsequent implementation of hardware system miniaturization using the microsystem 3D integration process.

This paper focuses on sorting out two backbone network variants’ development routes for CNNs and transformers based on deep learning methods for side-channel analysis. Combining parametric and quantitative structural analyses, it is preferred that improvement research be carried out on the structure of the continuation CNN variants. Firstly, the comparative reproduction of Zaid’s Efficient CNN and Wouters’ Simplified Efficient CNN will be carried out; second, ResNet will be designed and implemented based on residual structure and the improved design of feature-coded CNNs; finally, the four methods in DPA_ contest v4.1, AES_RD, AES_HD, and ASCAD public datasets will be used for extensive analysis experiments to explore the effects of six preprocessing roles at three scales and further explore the impact of data enhancement by dataset noise, offset, and amplitude scaling. The experimental results show that ResNet based on the residual structure and the coded feature CNN proposed in this paper exhibit better performance advantages than the previous methods. Preferring a preprocessing method for each dataset can continue to reduce the mean rank; continuing to overlay data enhancement methods can make the model easier to converge and increase the model’s generalization ability. To advance the research in the branch of CNNs and transformer variants in the SCA field, the model methods obtained from the above experiments and the datasets obtained from the processing have been made publicly available on GitHub.

The spiking convolutional neural network (SCNN) accelerator is well-suited for intelligent edge devices due to its low power consumption. However, there is still room for improvement in its power efficiency, particularly in terms of computation and memory optimization. In this paper, a temporal parallelism method is proposed to enhance power efficiency by minimizing unnecessary data movement. A streaming dataflow mechanism is introduced to pipeline the computations of convolution and pooling layers. Additionally, a configurable decomposition technique is designed to support arbitrary kernel sizes. The proposed accelerator is implemented on a Xilinx ZCU102 FPGA development board with a clock frequency of 200 MHz. Experiment results show that the proposed design consumes only 1.69 W of power while achieving a peak performance of 921.6 GOPS, resulting in a power efficiency of 545 GOPS per watt.

The application of deep learning in side-channel analysis faces critical challenges arising from dispersed public datasets—i.e., datasets collected from heterogeneous sources and platforms with varying formats, labeling schemes, and sampling settings—and insufficient sample distribution uniformity, characterized by imbalanced class distributions and long-tailed label samples. This paper presents a systematic analysis of symmetric cryptographic AES side-channel leakage datasets, examining how these issues impact the performance of deep learning-based side-channel analysis (DL-SCA) models. We analyze over 10 widely used datasets, including DPA Contest and ASCAD, and highlight key inconsistencies via visualization, statistical metrics, and model performance evaluations. For instance, the DPA_v4 dataset exhibits extreme label imbalance with a long-tailed distribution, while the ASCAD datasets demonstrate missing leakage features. Experiments conducted using CNN and Transformer models show that such imbalances lead to high accuracy for a few labels (e.g., label 14 in DPA_v4) but also extremely poor accuracy (<0.5%) for others, severely degrading generalization. We propose targeted improvements through enhanced data collection protocols, training strategies, and feature alignment techniques. Our findings emphasize that constructing balanced datasets covering the full key space is vital to achieving robust and generalizable DL-SCA performance. This work contributes both empirical insights and methodological guidance for standardizing the design of side-channel datasets.

Side channel Analysis (SCA) based on deep learning is highly sensitive to data quality. When using the ID leakage model as the labeling criterion in supervised classification problems, slight data imbalance issues arise, which can reduce analysis efficiency. Diffusion Models are an emerging class of generative models that offer more intuitive, stable, robust, and interpretable advantages compared to Generative Adversarial Network (GAN). To address data imbalance, we introduce a latent diffusion model based on U-Net that retains high-resolution information for the decoding process, thereby recovering detailed power consumption trace (hereinafter referred to as traces) information. Our model, named SCA Restoration with Diffusion Model (SCARefusion), comprises Conditional Nonlinear Activation Free Blocks (CNAFBlocks), downsampling, and upsampling modules. The network integrates the SimpleGate nonlinear activation function, enhancing model performance and computational efficiency, and improving adaptability to input data. This approach effectively generates balanced class data for labels, mitigating dataset imbalance and avoiding the instability of GAN training. In this paper, Correlation Power Analysis (CPA) is used to calculate and compare the correlation coefficients between hypothetical and measured traces to detect whether the generated data exhibit the same leakage points as the original data. Additionally, the effectiveness of the generated traces is validated using Convolutional Neural Network (CNN) attacks. Experimental results demonstrate that SCARefusion exhibits outstanding performance on the fixed-key ASCAD synchronous and asynchronous 50 dataset, capable of generating traces consistent with the leakage points of the original traces and successfully extracting the correct key. Furthermore, we discuss reducing the learning rate, optimizing network architecture, and other parameters to address loss oscillation issues during model training. These studies contribute to improving the performance and robustness of deep learning in SCA, effectively addressing data challenges.

In the surge of the digital era, the Metaverse, as a groundbreaking concept, has become a focal point in the technology sector. It is reshaping human work and life patterns, carving out a new realm of virtual and real interaction. However, the rapid development of the Metaverse brings along novel challenges in security and privacy. In this multifaceted and complex technological environment, data protection is of paramount importance. The innovative capabilities of high-end devices and functions in the Metaverse, owing to advanced integrated circuit technology, face unique threats from Side-Channel Analysis (SCA), potentially leading to breaches in user privacy. Addressing the issue of domain differences caused by different hardware devices, which impact the generalizability of the analysis model and the accuracy of analysis, this paper proposes a strategy of Portability Power Profiling Analysis (PPPA). Combining domain adaptation and deep learning techniques, it models and calibrates the domain differences between the profiling and target devices, enhancing the model’s adaptability in different device environments. Experiments show that our method can recover the correct key with as few as 389 power traces, effectively recovering keys across different devices. This paper underscores the effectiveness of cross-device SCA, focusing on the adaptability and robustness of analysis models in different hardware environments, thereby enhancing the security of user data privacy in the Metaverse environment.

With the rapid advancement of AI technology, the amount of data has been exponential growth, necessitating memory solutions that offer high speed, low energy consumption, non-volatility, and high reliability in memory cell. In this brief, we propose a 9T1R non-volatile SRAM (NVSRAM) based on Resistive Random Access Memory (RRAM) for low-power computing in memory (CIM). This cell combines the advantages of SRAM and RRAM to efficiently execute CIM. Additionally, it can power down during idle periods and back up data to RRAM, reducing SRAM standby power consumption. We provide a detailed introduction to the operating principles of three distinct modes: SRAM mode, NVSRAM mode, and CIM mode. Circuit simulations for each mode are presented to validate the functionality and performance of the design. Comprehensive performance evaluation tests reveal that the proposed unit achieves excellent results in terms of read static noise margin, energy consumption, and operation latency, underscoring its potential for advanced memory applications.

Field-programmable gate arrays (FPGAs) have garnered considerable interest and utilization, largely owing to their inherent flexibility and customizability. In this context, electronic design automation (EDA) technology serves as an instrumental facilitator for FPGA applications. Nevertheless, the emergence of hardware Trojans (HTs) represents a major vulnerability in FPGA security. To mitigate the risks associated with hardware Trojans, a formula has been devised to compute the controllability and observability of each signal within logic units in look-up table (LUT) netlists. Subsequently, a security verification methodology aimed at HT detection within these LUT netlists has been developed and incorporated into the EDA tool, BFDS. Detailed procedural steps for HT detection, including interactions with the graphical user interface, are elucidated. The efficacy of this embedded HT detection tool is substantiated through experimental validation. The results from these experiments confirm the capacity of the tool to successfully identify Trojans at the LUT-level netlist while seamlessly integrating into EDA toolchains, thereby enhancing the security of future FPGA design endeavors.

As the complexity of integrated circuit designs increases and the supply chain becomes more globalized, the threat of hardware Trojans has escalated, posing higher security requirements for Electronic Design Automation (EDA) software. This study introduces an FPGA integrated development environment and FPGA application development process that incorporates a hardware Trojan detection algorithm. It extracts features from the netlist after FPGA synthesis and utilizes Graph Convolutional Networks (GCN) to process the rich structural features in the netlist. To address the issue of imbalanced datasets, we incorporate the GraphSMOTE technique to enhance the model's generalization capability by synthesizing minority class samples. In the classification phase, an optimized GCN model is employed to determine whether each node is a Trojan node. Comparative experiments with several other models demonstrate a significant improvement in detection accuracy, achieving the highest F1 score and a high True Positive Rate (TPR), thereby validating the effectiveness and superiority of the GCN -based method in the field of hardware Trojan detection. This study not only enhances the security of the FPGA application development process but also provides new insights and tools for subsequent research in hardware security.

This article mainly focuses on the single event function interruption (SEFI) of 40 nm monolithic resistance random access memory (RRAM). Three dynamic modes were used in the experiment, including two read-only modes and write-read-read mode. The SEFI cross-section of three dynamic modes are similar. SEFI observed in the experiment is further divided into several types according to the characteristics of the error. The basic mechanisms of the different types of SEFI are analyzed and explained accordingly.

We investigated the heavy ion single-event effect (SEE) susceptibility of 40nm monolithic resistance random access memory (RRAM). The results show that single-event upset (SEU) of the memory cell occurred only in the write operation. The SEU of the cell was caused by the single-event transient (SET) of the peripheral circuit and the selection transistor. The dominant SEE type in dynamic modes was single-event functional interruption (SEFI). Some SEFIs could revert on their own in the next cycle, the rest needed a power cycle. We classified and analyzed all SEFIs into different types according to the number of cycles (or recovery mode) and the address distribution of the error data. Different types of SEFI are caused by SEU in different registers.

Interconnect resource(IR) test is one of the most crucial parts in Field Programmable Gate Arrays(FPGA) test. The Ford-Fulkerson algorithm of graph theory has already been applied in FPGA IRs testing. However, with the expansion of the FPGA scale, the efficiency of the Ford-Fulkerson algorithm is reduced. This paper improves the Ford-Fulkerson algorithm by dividing the FPGA IRs into three graphs, the horizontal graph, the vertical one and the oblique one, which reduces the algorithm complexity in large-scale FPGAs. This improved algorithm has been verified on mathematic model of XC5V110T FPGA IRs. Compared to the previous test methods, the efficiency of this improved algorithm has raised by 8 times.

Phase-locked loops (PLL) have been widely utilized in FPGA as an important module for clock management. PLL with dynamic reconfiguration capability is always welcomed in FPGA design as it is able to decrease power consumption and simultaneously improve flexibility. In this paper, a multi-functional PLL with dynamic reconfiguration capability for 65nm SRAM-based FPGA is proposed. Firstly, configurable charge pump and loop filter are utilized to optimize the loop bandwidth. Secondly, the PLL incorporates a VCO with dual control voltages to accelerate the adjustment of oscillation frequency. Thirdly, three configurable dividers are presented for flexible frequency synthesis. Lastly, a configuration block with dynamic reconfiguration function is proposed. Simulation results demonstrate that the proposed multi-functional PLL can output clocks with configurable division ratio, phase shift and duty cycle. The PLL can also be dynamically reconfigured without affecting other parts’ running or halting the FPGA device.

Partial reconfiguration is a technology that the different bitstream is loaded into reconfigurable region to realize the different functions. Partial reconfiguration be able to make reconfigurable time shorten greatly and implement time division multiplex access of logic resources. JTAG (Joint Test Action Group) is an essential module of FPGA (Field Programmable Gate Array), accomplishing testing, configuration and soon. As the result of supporting user-defined instruction, JTAG circuit has the good extensibility. In order to implement partial reconfiguration of logic resources, this paper puts forward dynamic reconfiguration instruction-DRP, and designs the JTAG circuit of accomplishing dynamic reconfiguration.

SRAM-based FPGA has become a core device in space application. However, based on CMOS technology, SRAM-based FPGA is sensitive for SEU effect. JTAG circuit is a significant module of SRAM-based FPGA, executing boundary-scan test and global configuration function. SEU effect can result in function disturbance of JTAG circuit. To adopt reasonable harden strategies for JTAG circuit, the paper puts forward an experimental scheme to evaluate the sensitivity of each module for SEU. Simulation results illustrate that the sensitivity of TAP Controller module is highest, 60% or more, compared with other modules. Finally, the paper proposes corresponding harden measures for sensitive module.

This paper presents a digitally controlled oscillator (DCO ) based on a multiplying delay locked loop (MDLL) ,and a DCO‐based configurable digital frequency synthesizer (DFS) is implemented .The output clock frequency is equal to the reference clock frequency multiplied by M divided by D .The multiplication ratio M and division ratio D can be programmed from 2 to 32 ,and 1 to 32 ,respectively .The frequency synthesizer achieves similar jitter performance as conventional MDLL .The DFS is implemented in TSMC 0 .13‐μm CMOS technology , with a layout area of 480 μm × 120 μm .The frequency range of the input and output clock are 1 ~ 270 M Hz and 15~ 400 MHz ,respectively .The measured phase noise is‐110 .01 dBc/Hz@ 1 MHz ,when the output clock frequency is 270 M Hz .