A novel in-fiber modal interferometer based on a long period grating (LPG) inscribed in a two-mode all-solid photonic bandgap fiber (AS-PBGF) is presented. After inserting a small piece of the AS-PBGF into two sections of standard single-mode fiber (SMF) via being spliced slight core offset, LPG is inscribed in the AS-PBGF. The LPG is especially designed to realize the coupling between two core modes of LP01 and LP11 in the AS-PBGF. Two core modes LP01 and LP11 of the AS-PBGF are excited firstly at the input spliced point and actualized energy exchange when they pass through the LPG. Then the two beams will interfere at the output spliced point to form a high-contrast in-fiber modal interferometer. The proposed interferometer has some advantages such as configuration compact, high interference contrast and the wavelength spacing well controlled by changing the position of the LPG without changing the total length of AS-PBGF.

A novel multi-parameter sensor based on a cascaded long-period fiber grating with two different periods is proposed and demonstrated. The sensing properties of long-period fiber gratings with different periods are investigated in detail which indicate that the long-period fiber gratings with different periods and the resonant peak positions have obvious sensitivity differences to the same changes of the external parameters. Such properties are useful for the design of multi-parameter sensor. Through the control of the fabrication parameters and the period, the fabrication of the cascaded long-period fiber gratings is achieved with the CO2 laser. The temperature and refractive index sensing properties of the cascaded long-period fiber grating are explored through experiments. Multi-parameter sensing is realized with such cascaded long-period fiber gratings in the experiments.

At present, there are many questions about the municipal bridge management and bridge safety accidents sometimes occur. How to strengthen the management of city bridges has become the governor's initial mission. The municipal bridge crisis management decision system integrates the geographic information system (GIS), the expert system (ES) as well as the database management system (MIS). The system has also established bridge spatial databases, the expert knowledge library, and the model and decision database. Through this system, we can make the accurate appraisal to the bridge technical position, propose the practical effective government measure and arrange the reinforcement at appropriate time. It may achieve the quickly turning of the decision, the automation and the systematization of the bridge management. According to the application of the system in Harbin, we have successfully made a dynamic, initiative; wide range and simple high efficiency bridge crisis management system come true.

A gray model(GM(1,1)) for predicting the camber level of long-span PC(pre-stressed concrete) continuous rigid frame bridge was established by using grey system theory.After being modified with residual GM(1,1),it was applied to the project of Longhua Songhuajiang Long-Span Bridge.The result shows that the prediction has a high accuracy and completely meets the requirements of the project.This method provides reference for the construction monitoring of the bridges with the same type.

The present highway bridge management which to a large extent relies on managers and technical personnel's experience is incompatible with the information age. The highway bridge management departments must rely on modern management thinking and advanced means of information processing. The highway bridge management information system taking Delphi evaluation as support model integrates data management, appraisal analysis, condition prediction, investment decision, dynamic image, multimedia and the GIS geography information processing. It can meet the highway bridge managers' needs as a whole. We elaborate the system constitution, the database design, as well as functional module design emphatically. Through the application of the system in Heilongjiang Province, the management of bridges has become highly effective, automated and systematic.

In February 2002, the Federal Communications Commission allocated huge frequency band (3.6 - 10.1 GHz) for UWB communication. Now many wireless communication experts are considering using a variety of techniques to utilize the huge bandwidth. Based on the fact that the large bandwidth of UWB waveform significantly increases the ability of the receiver to resolve the different reflections in the channel, most receivers are basically developed from the RAKE receiver [S. Roy et al., Feb 2004]. This paper proposes a modified receiver for UWB communication system. The receiver is composed of a symbol detector and a channel decoder separated by a deinterleaver. The principle of turbo-code and an iterative detecting-decoding process is applied in the receiver.

A Correlated Double Sample (CDS) Stage design is proposed for CMOS image Readout IC (ROIC) in this paper. A capacitor transimpedance amplifier (CTIA) stage is used as front stage. A parasitic insensitive Switch Capacitor (SC) circuit is used to realize CDS on chip. This circuit also supports Integration-While-Read (IWR) mode. Then channels low frequency noise is reduced and frame frequency is increased. A circuit based on this method is fabricated with 1.2 m CMOS technology. The simulation and measurement results are also given in this paper.

A high performance CMOS linear 288×4 readout integrated circuit(ROIC)is detailed in this paper.It is a large-scale mixed-signal circuit with time-delay integration(TDI)function to enhance the signal to noise ratio(S/N),and defective element deselection(DED)function to decrease the probability of bad columns.The other features include adjustable integration time,multi gain,bi-direction of TDI scan,super-sample,and electrical test.Digital I/O ports are designed to control its work mode.It is fabricated using 1.2μm double poly double metal(DPDM)CMOS technology.The measured power consume is about 24mW at 5 V supply.

This paper for the first time describes a programmable and high-precision temperature independent current reference without external component. It is based on SMIC 0.35/spl mu/m standard CMOS process with the supply voltage of 5V. In simulation results, when temperature changes from -20/spl deg/C to 100/spl deg/C, the circuit has a 46/spl mu/A output current with the variation of 0.1 /spl mu/A. The current's accuracy is about 18ppm//spl deg/C. It uses TC (temperature coefficient) compensation circuit by adding a positive TC current to a negative TC current. The circuit contains three blocks, and is designed to be used in an uncooled IRFPA ROIC (readout integrated circuit) as a reference current source.

An op-amp with a push-pull output stage for infrared focal plane array (IRFPA) readout integrated circuit (ROIC) is described in this paper. It works in the class AB mode with little die area. The op-amp is simulated by the SMIC 0.35-/spl mu/m CMOS process. The circuit is designed to operate from a single 5 V power and drive a capacitive load of 15 pF. The unity gain-bandwidth (GBW) is 30 MHz. the rising slew rate (SR) 34 V/s. and the falling slew rate (SR-) 39 V/s. The common-mode input and the output swing are almost 5 V.

A novel dual-window readout structure is presented in this paper. The ROIC with this structure can work in two modes: normal mode and windowing mode. The most special feature is that ROIC can readout two sub-arrays synchronously in windowing mode. Furthermore, the positions and sizes of these sub-arrays can be specified by users. This feature allows image system to trace two fast moving objects without using two ROICs. An experimental 64 X 64-pixel ROIC has been designed, and it will be fabricated with 0.5 mu m DPTM n-well CMOS process.

An improved CMOS snapshot readout structure called RRSCA (Reset Row-by-row Snapshot Charge Amplifier) for infrared focal plane array (IRFPA) is presented in this paper. The pixel circuits in RRSCA readout structure are reset row by row after each row's pixel signals were readout to the column stage in parallel and pixel circuit is very simple including only three MOSFETs. Thus, the RRSCA readout structure is very suitable for the readout circuit design with large-format and very small pixel size such as 30*30 or 25*25 μm 2 . An experimental 130 × 130 RRSCA chip has been fabricated with 1.2-μm Double-Poly Double-Metal (DPDM) n-well CMOS technology. Both simulation results and experimental results are presented.

This paper details a high performance CMOS linear readout integrated circuit (ROIC) and the measured result. This ROIC realizes time-delay integration (TDI) to enhance the signal to noise ratio (S/N), and defective element deselection (DED) to decrease the probability of bad columns. The Other features include adjustable integration time, multi gain, bi-direction of TDI scan. super-sample, and electrical test. It is fabricated using 1.2-μm double poly double metal (DPDM) CMOS technology. The total power consumption is about 24 mW at 5 V supply voltage.

A novel readout structure called Forward-Backward-Asynchronous-Reset (FBAR) structure is presented in this paper. This readout structure is used in high performance CMOS readout integrated circuits (ROIC). Using asynchronous reset structure can increase the column OPA's smallest settling time without decreasing frame's readout frequency. By increasing smallest settling time, a low-power column OPA with power dissipation=78 μW can satisfy fast readout speed. While in typical synchronous reset structure, the column OPA's power dissipation may exceed 200 μW to meet readout speed. This improvement can save more than 50% power dissipation of the column readout stage. An experiment ROIC chip using FBAR structure has been fabricated with 1.2 μm DPDM n-well CMOS technology. Testing result shows the total active chip power dissipation is 25 mW.