This work presents a 256-channel neural probe for closedloop DBS with per-channel low-power in-situ dual-looposcillator ADCs. Two operating modes are supported: neural recording with baseline stabilization and stimulation with synchronous monitoring. The $0.0010 \text{mm}^{2} /$ channel probe consumes $4.32 \mu \mathrm{W} /$ channel and achieves $3.68 \mu$ Vrms input-referred noise over a 10 kHz bandwidth. The area-energy efficiency FoM ($0.21 \text{fJ} \cdot \text{mm}^{2} /$ step) and NEF (2.69) represent state-of-the-art performance.

This paper presents a 16-bit, energy-efficient, fully dynamic successive-approximation-register (SAR) capacitance-to-digital converter (CDC) for single-ended capacitive sensors. A system-level correlated-double-sampling (CDS) scheme is proposed to suppress errors arising from comparator offset, low-frequency noise, and external interference. The delay time characteristics of the inverter-based amplifier (FIA) comparator are characterized for the first time, and an optimal delay time is determined through simulation. An LSB-repetition scheme improves low-noise performance. Dual digital-supply technique reduces the power consumption of the digital circuitry and also extend the delay time of digital delay elements with minimal power overhead, thereby improving energy efficiency. Fabricated in a 180-nm CMOS process, the CDC is validated using a capacitive MEMS pressure sensor, achieving a best resolution of 0.27 fF and a signal-to-noise ratio (SNR) of 82.6 dB among SAR CDCs. Consuming 2.85 mu W with a 56 mu s conversion time, it achieves a Walden figure-of-merit ( FoM(w) ) of 15 fJ/step. The CDC attains a DNL of -0.76/+0.85 LSB and an INL of -9.16/+9.15 LSB without calibration. Experimental results demonstrate more than 16 & times; improvement in interference rejection at 100 Hz and more than 7 & times; improvement under 1000 Hz, compared to a non-CDS implementation.

This paper presents an event-driven, dual-mode cryogenic infrared vision sensor that features a two-step time-encoding (TE) analog-to-digital converter (ADC) and a high-speed frame difference (FD) for motion detection. To enable always-on scene-adaptive motion perception with power optimization, the vision sensor is reconfigurable, supporting two operation modes: 1) Precise Imaging (PIM) and 2) Motion Detection (MD). In PIM mode, a two-step TE ADC is proposed for small-pixel-pitch infrared focal plane arrays (IRFPAs). The coarse conversion utilizes pulse frequency modulation (PFM) with an area-efficient true single-phase clock (TSPC) counter. This PFM employs a non-periodic-reset architecture to enable multi-subframe fusion and fine conversion of time-to-first spike (TFS), thereby improving the signal-to-noise ratio (SNR) within a limited pixel area. In MD mode, a high-speed FD-based 1.5-bit event detection is implemented, using subframe coarse conversion without incurring additional memory cost or frame-rate loss. Compared with PIM mode, MD mode reduces power consumption by approximately 40% by deactivating fine conversion and partial output channels. A 1280 x 1024 prototype with a 15-mu m pixel pitch was fabricated using a stacking process, in which the digital readout integrated circuit (DROIC) was implemented in a 0.18-mu m CMOS process and interconnected with the HgCdTe IRFPA via indium bumps. In PIM mode, the prototype achieves 83.2dB SNR with a power consumption of 115.4 mW at 30.5 frames per second (fps) (1.49 pJ center dot mu m(2)/step). In MD mode, with an 8-bit coarse conversion for event detection, the sensor consumes 58.83 mW at 976.6 fps (3.5 fJ/pixel-event), achieving the best event FoM among reported event-driven infrared vision sensors.

This paper presents a Zoom capacitance-to-digital converter (CDC) for single-ended capacitive sensors. An adaptive-load scheme proposed reduces gain loss and signal attenuation in pseudo-differential Δ∑M. A configurable Zoom CDC introduced enhances performance at moderate resolution. The prototype is validated using two sensors with a 43.3-pF capacitance range, achieving 1) 63.9-aF resolution (17.6-bit ENOB) and 176.4 dB FoMs in Zoom mode, and 2) 4-μs response time, 173.8-fJ/conversion-step, and power-bandwidth scalability in SAR mode.

This article presents a 16-channel front-end application-specific integrated circuit (ASIC) for cryogenic infrared focal plane arrays (IRFPAs), targeting the critical constraints of sensor interface compatibility and system-level detection sensitivity. To address the wide output commonmode (CM) voltage variations inherent in various IRFPA readout integrated circuits (ROICs), an adaptive capacitive level-shifting (ACLS) programmable gain amplifier (PGA) is proposed. By reconfiguring the negative-path sampling capacitor array as an 8-bit capacitive digital-to-analog converter (CDAC) for adaptive level shifting, the PGA achieves a rail-to-rail input CM range, effectively maximizing the sensor system dynamic range (DR) without additional area or power overhead. Furthermore, a calibration-free 16-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) based on a capacitor-resistor (C-R) hybrid DAC is proposed to ensure high intrinsic linearity. A 5-bit flash sub-ADC sharing the resistor ladder with the C-R hybrid DAC is integrated to accelerate MSB coarse quantization, thereby relaxing the RDAC settling constraint for 1-MS/s operation while minimizing static power consumption. The calibration-free architecture avoids the per-channel calibration overhead that scales poorly with channel count, ensuring readout consistency across the 16-channel array. Four on-chip low-dropout regulators (LDOs) and four voltage driver buffers associated with an 8-channel 12-bit DAC are integrated to locally regulate supply and bias voltages in close proximity to the IRFPA. This on-chip power management decouples the supply rails from cryogenic-to-ambient interconnect parasitics, suppressing voltage ripples and minimizing thermal loading through cryostat feedthroughs. Fabricated in a 180-nm CMOS process, the ASIC occupies 39.6 mm(2). Measured at 77 K, the chip exhibits a total power consumption of 97.54 mW. Operating at 1 MS/s with a 3.3-V supply, the SAR ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 81.08 dB. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are -0.61/+0.96 LSB and -4.26/+4.29 LSB, respectively. Each ADC channel consumes 1.92 mW, yielding a Schreier figure of merit (FoMS) of 165.2 dB. Validated with a long-wave IRFPA, the ASIC enables high-fidelity cryogenic imaging, demonstrating its effectiveness in high-precision cryogenic sensing systems.

This brief presents a 1280 & times; 1024 pixel-array, 10 & micro;m-pitch digital readout integrated circuit (DROIC), fabricated in a 180-nm CMOS process and hybrid-integrated with an InGaAs sensor array for megapixel-level short-wave infrared (SWIR) imaging. The DROIC employs a column-parallel analog-to-digital converter (ADC) architecture, in which a 2-bit time-to-digital converter (TDC) is incorporated into a 12-bit single-slope (SS) ADC to quantize the residual signal. A chip-shared multiphase clock generator scheme is adopted to provide uniform phase references with small area and low power overhead. To address coarse-fine stitching errors caused by chip-shared multiphase clock distribution, a self-correcting phase-coded stitching scheme is proposed. The proposed selfcorrecting phase-coded stitching scheme mitigates SNR degradation and improves column-to-column uniformity by suppressing jump code errors. The hybrid-integrated SWIR focal-plane array (FPA) achieves an array-averaged SNR of 83.44 dB and a random noise of 4.2 e(rms)(-), while the measured dark fixed-pattern noise (FPN) is 0.11%. The FPA consumes 408 mW at a frame rate of 60 Hz, achieving a power efficiency of 427.16 fJ/LSB. These results demonstrate excellent noise performance, low FPN, and high energy efficiency for megapixel-level SWIR imaging.

This article presents an event-driven, high-speed readout integrated circuit (ROIC) with in-sensor trace detection capabilities for cryogenic infrared focal plane arrays (FPAs), aimed at the next-generation smart infrared motion perception applications. To achieve high accuracy and agile motion recognition with low power consumption and bandwidth requirements, we propose an event-driven image and trace detection method. The proposed pixel consists of two key components: 1) event detection (ED) and 2) imaging and trace detection (ITD). In response to the demands of cryogenic infrared FPAs, we introduce a synchronized linear response ED circuit that encodes temporal variations in infrared radiation into 1.5-bit events. Additionally, we propose an in-sensor trace generation method that fuses spatial and temporal information streams, enabling high-accuracy motion recognition while reducing computational and power requirements. When coupled with a postprocessor, the event-driven mechanism reduces the need for extensive motion localization and imaging efforts in motion analysis. Meanwhile, the trace information generated by the ITD module further enhances motion recognition accuracy for identified objects of interest. The ROIC provides a spatiotemporal redundancy compression and an energy-efficient solution for infrared motion perception applications. A prototype based on a 16x16 array with a 20- mu m pixel pitch, fabricated using a 0.18- mu m 1P5M CMOS process, demonstrates event-driven motion perception, consuming 11.93 mW (40.75 mu W for the array and 10.95 mW for the output buffers) at a 12.2-kHz event and image frame frequency. Detailed test and measurement results of the prototype are provided.

This article presents a novel data acquisition system (DAS) designed for area-sensitive applications, including automotive instrumentation, launch vehicles, and satellites, which require efficient area utilization and full-swing input/output capabilities for diverse sensors. Traditional approaches to achieving full swing, such as using CMOS input transistors or generating negative voltage via charge pumps, either result in high harmonic distortion (HD) or complicate chip design. To address these challenges, we propose a complementary analog front-end (CAFE) that shifts the input signal by a fixed voltage, enabling operation in a more linear region while employing feedback to minimize HD. The system incorporates two analog-to-digital converters (ADCs) that convert the input signal and subtract the digital output of the common mode voltage (V-CM), facilitating effective data fusion for complete AD conversion. Fabricated using a 180-nm 1P5M BCD process, the DAS consumes 118.81 mW from a 5.0-V power supply, providing 64 channels in a compact area of 4.0 x 3.2 mm. At a sampling rate of 1 MS/s, it achieves an effective number of bits (ENoBs) of 13.16, with a power consumption of 1.856 mW per channel and a dynamic range of 83.3 dB, resulting in an impressive figure of merit per channel (FoM(S)/Ch) of 165.3 dB.

Long-wavelength (LW) cryogenic (from 80 down to 40K) infrared focal plane arrays (IRFPAs) are extensively employed because of their sensitivity and rapid response. Readout circuits (ROIC) with high dynamic range (HDR) can significantly improve the signal-to-noise ratio (SNR) of LW-IRFPAs due to enhancement of well capacity. However, neither conventional current-voltage nor current-frequency modulation can avoid analog circuits, making the ROIC susceptible to interference [1]–[8]. In these ROICs, active analog circuits are usually the primary power consumption item. Moreover, the long data transfer bus with a high swing across the pixels consumes power and introduces crosstalk. To address these issues, an LW-IRFPA architecture with pixel-paralleled light-driven current-to-phase A/D conversion (IP-ADC) is implemented in this work. The key circuit includes: 1) a light-current-controlled oscillator (LCO) based modulator for IP-ADC that is powered only by photocurrent without extra power supply; 2) a phase-reconstruction circuit to enhance low-light performance while reducing quantization noise by sub-phase extraction; 3) a pixel-level 20b asynchronous gray-code counter for high equivalent full well capacity during phase quantization; and 4) a low-swing bus data transfer circuit to reduce transmission power consumption and crosstalk. Overall, this work demonstrates a $320\times 256,\ 30\mu \mathrm{m}$ pixel pitch, $10.55\mu\mathrm{m}$ wavelength quantum-well infrared photodetector (QWIP) IRFPA. The ROIC used in IRFPA is fabricated in a $0.18\mu \mathrm{m}$ standard CMOS process. The performance of this IRFPA achieves 120.4dB HDR, 2.2mK noise equivalent temperature difference (NETD) within a typical 6.9mW power consumption.

This article presents a four-channel interface application-specific integrated circuit (ASIC) for infrared focal plane arrays (IRFPAs), where each channel integrates a programmable gain amplifier (PGA) with wide-range input common-mode adjustment capability and a 16-bit hybrid analog-to-digital converter (ADC) with resistor-sharing technique (RST). The flash stage of the ADC performs 5-bit most significant bits (MSBs) conversion, whose results are transferred to thermometer-coded capacitor array in the successive approximation register (SAR) stage, ensuring high linearity while maintaining conversion speed. This hybrid architecture of the ADC uses the RST by sharing the resistor ladder between the flash and SAR stages, reducing power consumption. The interface ASIC fabricated in the 180-nm CMOS technology achieves an input common-mode adjustment range of 0.169-3.269V. Operating at 2 MS/s with a 3.3-V supply, it achieves an 88.1-dB signal-to-noise-and-distortion ratio (SNDR) and consumes 13.97 mW/channel. The Schreier figure-of-merit (FoM) of the ADC reaches 171.2 dB/channel. Measured differential and integral nonlinearity (DNL/INL) are -0.38/+0.49 least significant bits (LSBs) and -2.2/+1.4 LSB, respectively.

This brief presents a cryogenic voltage reference circuit designed to operate effectively across a wide temperature range from 30 to 300 K.A key feature of the proposed design is utilizing a current subtraction technique for temperature com-pensation of the reference current,avoiding the deployment of bipolar transistors to reduce area and power consumption.Implemented with a 0.18-µm CMOS process,the circuit achieves a temperature coefficient(TC)of 67.5 ppm/K,which was not achieved in previous works.The design can also attain a power supply rejection(PSR)of 58 dB at 10 kHz.Meanwhile,the aver-age reference voltage is 1.2 V within a 1.6%3σ-accuracy spread.Additionally,the design is characterized by a minimal power dis-sipation of 1 µW at 30 K and a compact chip area of 0.0035 mm².

This brief presents a 12-bit low-power successive-approximation-register (SAR) capacitance-to-digital converter (CDC) for capacitive pressure sensors. It adopts a capacitance-to-voltage front-end (CVFE) scheme to decouple the capacitive digital-to-analog converter (CDAC) from the sensor capacitor, enabling a large swing of the SAR analog-to-digital converter (ADC) and a wide capacitance sensing range. To improve power efficiency, this brief proposed a top and bottom sampling (TBS) for CVFE circuit to achieve a single-ended sampling while differential conversion. The TBS includes only one sampling phase, which relaxes the amplifier's bandwidth requirements, thereby reducing the power consumption of the CVFE. The prototype chip was fabricated using a 180-nm CMOS process. The measured capacitance resolution is 1.76 fF and the measurement capacitance range is from 0.63 pF to 38.37 pF. The proposed CDC consumes 3.90 mu W with a 128 mu s conversion time, bringing a power efficiency of 80.6 fJ/conversion-step.

An interface chip for atomic sensor with highly integration using multi-voltage reference is proposed in this brief. Atomic sensors are growing fast in the direction of miniaturization and convenience, and higher demands are placed on integration and low power consumption. Atomic sensors are multi-loop feedback system, the interface circuit contains signal detection and drivers, which serve to implement temperature stabilization, vertical-cavity surface-emitting laser (VCSEL) locking, voltage controlled crystal oscillator (VCXO) regulation, and magnetic field control. Reference voltage buffer (RVB) has been proposed based on the characteristics of the atomic sensor system, which can be used for the high implementation of each driver and the digitization of the signal detection circuit, reducing the power consumption and improving integration. The proposed interface chip is fabricated in 180nm CMOS technology. Measurement results show that the signal detection circuit has a programmable gain of 30 dB to 60 dB and a bandwidth of 120 Hz to 7k Hz. The equivalent input current noise density (EICND) measurement results for the interface chip at maximum programmable gain is 1.41 pA/√Hz@1k Hz. The ADC achieves 75.8 dB signal-to-noise ratio (SNR) at 976.8066 Hz input sine signal while operating at sampling rate of 16 kS/s.

This article introduces a high-voltage (HV) compliant, energy-efficient current-mode stimulator featuring a proposed boost-based dynamic voltage supply (DVS) to minimize the voltage dropout. The stimulator employs an activate-on-demand asynchronous strategy, instructing the boost converter to generate the dynamically increased high voltage that tracks the electrode's voltage drop, thus achieving a near-adiabatic stimulation. The strategy relies on measuring the boost's varying voltage conversion ratio (VCR), which is facilitated by an 8-bit voltage ratio quantizer (VRQ) proposed in this article. Furthermore, the boost converter employs a low-power, fast-speed, HV gate driver (HVGD) to control its p-type power switch that connects the inductor to the HV output. This article also presents a dedicated digital circuit that generates the pulse signals for controlling the n-type power switch and the HVGD. This digital circuit is driven by a five-phase clock from a current-starved ring oscillator. A highly efficient rotationally symmetric level shifter is utilized for the ring oscillator's output, translating its level and improving its rise/fall time. The boost converter reaches a peak efficiency of 90.2%, enabling the stimulator to achieve an end-to-end energy efficiency of up to 86% during a biphasic stimulation of 6 mA. The stimulator IC, fabricated using 0.18-m bipolar-CMOS-DMOS (BCD) technology, occupies a compact area of 2.16 mm(2). It exhibits low static power consumption at 1.78 mu W, promising battery-powered implants with an extended lifetime and a reduced form factor.

This paper designs a 12-bit SAR ADC in 0.18-μm CMOS technology. To save power and suppress the effect of capacitor mismatch, Vcm-based split MSB switching technology is used. To reduce the capacitance of CDAC and achieve better matching, a novel layout for segmented CDAC is proposed, which significantly reduces the parasitic capacitor at the top plate of sub CDAC. At a 3.3-V supply and a sample rate of 1 MS/s, the SAR ADC has an ENOB of 11.2 bits without missing any code.

TEC-less bolometric imagers have the advantages of size, weight, power, and cost (SWaP-C). However, the imagerfs responsivity drifts dramatically with the substrate temperature, resulting in scene dynamic range (DR) degradation. This brief presents a 120∘C operating range TEC-less bolometric imager with ultra-low responsivity drift. The proposed imagerfs low responsivity temperature coefficient is obtained by summing the positive and negative temperature coefficients. In the readout circuit, a poly resistor and a bolometer resistor are used in series as the feedback resistor of the pre-amplifier to accomplish the above summing. The proposed readout circuit is a low-cost improvement and hardly increases the complexity. A 12 μm pixel pitch 640×512 resolution vanadium oxide (VOx) bolometric imager is implemented for verification. Measurement results show that the responsivity drift is less than 20% within the 120∘ temperature range, while the drift is higher than 90% without compensation. The proposed imagerfs measurement noise equivalent temperature difference (NETD) is 45 mK, demonstrating good NETD performance. The proposed imager is suitable for TEC-less wide temperature range low SWaP-C applications.

This brief presents a low-power, high-precision neural recording circuit for closed-loop deep brain stimulation (DBS). It adopts a switched-capacitor (SC) low-pass filter (LPF) with the double sampling technique to efficiently attenuate high-frequency noise and signal with precise cut-off frequency. To improve power efficiency, this brief proposes a multi-sampling successive approximation register (SAR) analog-to-digital converter (ADC) for quantization. It synchronously samples LPF's output, thus maximizing LPF's power utilization. The single-channel prototype chip was fabricated in a 180 nm CMOS process. The neural recording channel consumes 31.98 mu W from a 1.8-V supply. The proposed 11-bit multi-sampling SAR ADC features an ENOB of 10.38 bits at a sampling rate of 20.83 kS/s. The measured input-referred noise of the neural recording channel is 1.52 mu Vrms for 1 Hz-300 Hz band and 1.96 mu Vrms for 300 Hz-6.5 kHz band, respectively, promising a high precision for neural recording in closed-loop DBS systems.

This paper presents a low-power and energy-efficient capacitance-to-digital converter (CDC) for a single-end sensor based on correlated double sampling (CDS) technology. The CDS is accomplished by two opposite conversions, which reuse the comparator, C-SENS, and C-DAC. The proposed CDC eliminates the parasitic-dependent error caused by the comparator's offset without extra consumption through the CDS. The simulation results show that the CDC can eliminate low-frequency interference and achieve anti-common-mode interference capabilities similar to differential circuits. To achieve low noise and high energy efficiency, the CDC employs a floating inverter amplifier (FIA) as the pre-amplifier of the comparator. Implemented in a 0.18 mu m CMOS process, it consumes 0.91 mu W from a 1.2 V supply. The simulation results show an effective number of 11.69 bits and an energy efficiency of 27.5 fJ per conversion step.

This paper presents an event- driven readout integrated circuit (ROIC) for imaging and target-tracking infrared focal plane arrays (IRFPAs). The pixel circuit consists of event detection (ED) and imaging and trace detection (ITD). Based on the dynamic vision sensor (DVS) structure, ED encodes the temporal changes of infrared radiation into synchronized 1.5-bit events and transmits them to the off-chip postprocessor. When a moving target is recognized, the region of interest (ROI) window address will be feedback to ROIC and read out the image and trace information provided by ITD, which is based on infinite impulse response in the analog domain. These absolute intensities and multi-frame fused trace allow the post-processor to complete high-accuracy agile action recognition. This ROIC provides a spatiotemporal redundant compression and energy-efficient solution for fast-moving object detection and analysis. A prototype based on a 16x16 array of 20 mu m pixel-pitch has been fabricated using a 0.18 mu m 1P5M CMOS process, consuming 11.93mW@12.2kHz event and image frame frequency. Detailed test and measurement results of the prototype are presented.