This paper presents a tunable parametric notch filter based on a double-pump parametric-mixing architecture that enables on-chip Q-enhancement. A primary pump generates a frequency-dependent positive conductance at the signal frequency, producing a tunable absorption notch, while a secondary pump introduces negative resistance at the idler frequency to compensate resonator loss and enhance selectivity. This mechanism, referred to as parametric mixing, enables active control of the effective quality factor of the idler resonance without external high-Q components. The proposed architecture is implemented as a fully integrated GaAs MMIC and operates over a tuning range of 1.3-2.1 GHz. Measurements show that single-pump operation produces a tunable notch with 4.5-6 dB attenuation, while activation of the second pump increases the notch depth to 13.5-25 dB and reduces the fractional bandwidth to 5.5-6.5%, consistent with Q-enhanced behavior. The device also exhibits a low-loss through response when both pumps are disabled, enabling a true notch-off state. Measured S-parameters show that the double-pump operation substantially improves notch depth and fractional bandwidth, while simulation-based effective-Q extraction supports the interpretation that this improvement results from idler loss compensation, providing a compact and scalable solution for high-selectivity reconfigurable RF filtering.
This paper presents a tunable parametric notch filter based on a double-pump parametric-mixing architecture that enables on-chip Q-enhancement. A primary pump generates a frequency-dependent positive conductance at the signal frequency, producing a tunable absorption notch, while a secondary pump introduces negative resistance at the idler frequency to compensate resonator loss and enhance selectivity. This mechanism, referred to as parametric mixing, enables active control of the effective quality factor of the idler resonance without external high-Q components. The proposed architecture is implemented as a fully integrated GaAs MMIC and operates over a tuning range of 1.3-2.1 GHz. Measurements show that single-pump operation produces a tunable notch with 4.5-6 dB attenuation, while activation of the second pump increases the notch depth to 13.5-25 dB and reduces the fractional bandwidth to 5.5-6.5%, consistent with Q-enhanced behavior. The device also exhibits a low-loss through response when both pumps are disabled, enabling a true notch-off state. Measured S-parameters show that the double-pump operation substantially improves notch depth and fractional bandwidth, while simulation-based effective-Q extraction supports the interpretation that this improvement results from idler loss compensation, providing a compact and scalable solution for high-selectivity reconfigurable RF filtering.
In deep learning, efficiency gets more and more important to compensate for the ongoing growth in model sizes and applications. Neuromorphic hardware has long been advocated as an upcoming alternative to deep networks, taking inspiration from the brain for achieving unprecedented energy efficiency. However, demonstrations of these gains only recently began to grow in complexity and real-world applicability. With SpiNNaker2, we present a chip that bridges the gap between deep networks and neuromorphic computing and allows for flexible exploration of computing approaches that combine both worlds. It features 152 processing elements equipped with an ARM M4F processor and dedicated accelerators, an extended SpiNNaker routing fabric for scalable event-based communication and a range of external interfaces for system integration, including Gbit Ethernet and an LPDDR4 memory interface. We demonstrate performance and efficiency of the SpiNNaker2 chip for neuromorphic and deep network workloads, as well as novel event-based computing approaches. For deep network workloads, the chip achieves up to 4.5 TOPS in high performance mode and up to 2.7 TOPS/W efficiency in high efficiency mode for INT8 workloads. The chip supports spiking neural networks with >150 000 neurons and > 1.8 billion synaptic events/s when simulated with a 1 ms time step. Its low baseline power of less than 250 mW allows for efficiency even under varying workload conditions, allowing to explore sparse and event-based modes of computation. All this demonstrates the chip’s capabilities as a universal hardware platform for scalable brain-inspired computing and its combinations with mainstream deep network approaches.
We present a standards-compliant IEEE 754 FP32 Gaussian random number generator (GRNG) for FPGA based on the Marsaglia–polar method, designed to deliver verifiable tails and reproducible floating-point semantics for scientific and security-relevant workloads. The key contribution is a streaming, tokenized polar architecture that (i) cleanly separates the uniform feeder from the Gaussian transform core (AES–CTR by default, swappable by threat model), and (ii) uses IEEE-field-based accept–reject gating to avoid invoking expensive {ln,÷, √·} stages on invalid samples, improving pipeline efficiency while preserving IEEE 754 behavior. We complement empirical ULP/relative-error checks with an explicit conditioning-based stability analysis of the ln(s) → /s → √· chain and validate statistical fidelity via histograms, Q–Q plots, Kolmogorov–Smirnov distances, independence checks, and large-N tail stress testing. Application-level evaluations (BER-over-AWGN for BPSK and DP-style Gaussian noise injection in ML) include software baselines and confidence bounds to demonstrate system-level fidelity. On a Xilinx Artix–7, the post-route design meets 400MHz and produces two samples per cycle (800MS/s) using 1535 LUTs and 12 DSPs, with total power 0.264W (dynamic 0.132W); an ASIC-scaled projection to 22nm provides contextual throughput comparison.
This paper presents a unified and flexible framework for implementing auditory-inspired filters based on the Gamma Kernel. The proposed structure enables both Gammatone and Gammachirp filters to be realized using the same configuration, providing a compact and versatile design suitable for auditory modeling and signal processing applications. This is achieved through the utilization of a curve-fitting technique in MATLAB that approximates the Laplace transform of each filter’s impulse response, leading to a rational integer-order transfer function. By adjusting the coefficient values of this function both Gammatone and Gammachirp filter-banks can be implemented, significantly simplifying the design and tuning process. An auditory filter example implemented on a Field Programmable Analog Array (FPAA) device is demonstrated, where magnitude and impulse responses are both evaluated.
This paper presents a single-lead, ultra-low-power ECG system-on-chip (SoC) for real-time acquisition and multi-class arrhythmia detection at 1.0 V. The SoC integrates a chopper-stabilized analog front end (AFE), an 11-bit Successive Approximation Register Analog-to-Digital Converter sampling at 7.812 kS/s (synchronized to the gain amplifier's mid-interval sampling), hardware feature extraction, an event-driven one-vs-all (OvA) linear support vector machine (LSVM) classifier, and an on-chip patient-adaptive false-alarm suppression block (PACER). Robust acquisition is achieved by preserving 0.1-50 Hz ECG content in the analog path and applying a light 0.5-45 Hz digital band-limiting before feature extraction. A compact five-feature vector (R-wave, S-wave, T-wave, R-R interval, Q-S interval) enables a shared-multiply-accumulate OvA LSVM implementation with minimal area/energy. Fabricated in 0.18 mu m CMOS, the SoC demonstrates 0.418 J per classification with 1-2 ms compute latency and 96.2% system-level alarm-event accuracy under inter-patient (patient-level) evaluation on MIT-BIH and Creighton University Ventricular Tachyarrhythmia datasets and achieves > 99% alarm-event-level false-alarm reduction through an on-chip severity-based PACER block. The complete chip measures 1.2 mm & times;0.6 mm and sustains 5.36 mu W steady-state monitoring power at 1.0 V, illustrating an algorithms-in-hardware approach to clinically relevant, long-term wearable ECG monitoring.
The goal of this research is to trace the evolution and development of multiplier-less architectures, utilizing the Canonical Signed Digit representation from the 1970s to modern implementations through 2025. This paper examines key advances in hardware optimization that aim to reduce computational complexity, power consumption, and area usage. This paper covers the use of the CSD in diverse applications such as digital filters, image coding, and neural network accelerators. Recent advances in the use of the CSD for achieving multiplier-less architectures are highlighted, and research gaps and future work directions are discussed. The main focus is on the role of CSD in enabling efficient low-power arithmetic in real-time embedded systems and AI applications, and its relevance in emerging technologies.
The goal of this research is to trace the evolution and development of multiplier-less architectures, utilizing the Canonical Signed Digit representation from the 1970s to modern implementations through 2025. This paper examines key advances in hardware optimization that aim to reduce computational complexity, power consumption, and area usage. This paper covers the use of the CSD in diverse applications such as digital filters, image coding, and neural network accelerators. Recent advances in the use of the CSD for achieving multiplier-less architectures are highlighted, and research gaps and future work directions are discussed. The main focus is on the role of CSD in enabling efficient low-power arithmetic in real-time embedded systems and AI applications, and its relevance in emerging technologies.
By design, solid-state relays are not subject to mechanical wear, exhibit no contact bounce or arcing, and are immune to shock and vibration. These properties enable their replacement of electromechanical relays in many applications. However, to fully exploit their potential, semiconductor-based relays must continue to be improved in terms of cost, area, and performance. This paper presents the functionality and structure of a low-cost solid-state relay. Two n-channel MOSFETs connected in anti-series are used as power switches, with their common gates driven by a “constant-current-injection” (CCI) control scheme. The resulting bidirectional semiconductor switch provides no galvanic isolation between the control and power stages, enabling a cost-efficient and space-saving solution. The proposed circuit is simple to implement, based on readily available components, and flexibly scalable in terms of current, voltage, and switching speed. In addition to the circuit description and the turn-on and turn-off behavior, a prototype implementation of the bidirectional relay is presented, which is targeted for cell selection in active battery management systems.
Reconfigurability and self-optimization are becoming essential in radio frequency integrated circuit (RFIC) design due to the rapid growth of wireless devices and dynamically changing spectrum conditions. This work presents a CMOS mixer with a wide digitally tunable bias current, enabling machine learning (ML) assisted adaptation within a self-optimizing receiver (RX) architecture. The proposed mixer topology incorporates a programmable helper current (PHC) circuit to preserve voltage headroom across a broad tuning range while dynamically minimizing power consumption according to system-level requirements. Post-layout results demonstrate up to 8× power reduction while maintaining an input third-order intermodulation intercept point (IIP3) greater than −2.4 dBm across all operating modes. The adaptive mixer topology is integrated into a fully tunable RX front-end consisting of a digitally programmable LNA, in-phase/quadrature-phase (I/Q) mixers, and a tunable low-pass filter. A hardware–software co-simulation framework is introduced, combining a spectrum-agile GNU Radio transmitter, the CMOS adaptive front-end, and an FPGA-based real-time demodulation engine for system-level performance extraction. The front-end achieves a power tuning range of 0.73–3.60 mW, with corresponding conversion gain of 20–33.6 dB, noise figure of 12.2–30.5 dB, IIP3 of −20 to −7.6 dBm, and 1-dB compression point of −27.4 to −14.7 dBm. Wireless system-based simulations resulted in error vector magnitudes ranging from 4% to 18.7%, demonstrating effective power–performance tradeoffs. The results validate the wide-range adaptive power scaling capability with preservation of adequate linearity and noise performance under varying wireless conditions.
A new CMOS-only voltage reference, operating in current mode and leveraging subthreshold MOSFETs, is presented in this paper. In contrast to conventional solutions that sum PTAT and CTAT currents to provide a constant voltage reference, the proposed design introduces a zero temperature coefficient current by subtracting two CTAT currents-representing a key design novelty. Moreover, the presented approach does not use any trimming scheme to generate the output voltage. By eliminating bulky Bipolar Junction Transistors (BJTs), the circuit significantly reduces both area and power consumption while retaining robust performance in harsh environments over a temperature range from -20 degrees C to 150 degrees C. Fabricated in TSMC 130-nm CMOS technology, it delivers an output voltage near 610 mV with a measured temperature coefficient (TC) ranging from 188 ppm/ degrees C to 212 ppm/ degrees C across different chips. Owing to its current-mode operation, the voltage reference level can be readily adjusted through the decoder's inputs, providing flexibility for a variety of applications. Measurement results confirm a power supply rejection (PSR) of -73 dB and a quiescent current of 3.2 & micro;A from a 1.2 V supply, making this trimless voltage reference an attractive option for compact, low-power systems
This paper presents a ping-pong current-integrating feed-forward equalizer (PPI-FFE) architecture for high-speed wireline receivers, enabling the realization of multi-tap analog FFE with reduced hardware complexity. By leveraging time-interleaved integration and ping-pong operation, the proposed architecture decouples the number of FFE taps from the number of first-rank track-and-hold (T/H), significantly reducing the required number of jitter- and skew-sensitive sampling elements and unit Gm-cells compared to conventional interleaved discrete-time FFE implementations. As a result, the architecture offers a more compact and routing-friendly solution, mitigating parasitic and matching challenges in analog FFE design. As a proof of concept, a reconfigurable 4-tap PPI-FFE is implemented in 22-nm FDSOI technology targeting a 112-Gb/s PAM-4 receiver. Post-layout simulation results demonstrate effective ISI mitigation over a 32-dB-loss channel at Nyquist, with 26 mW power consumption for the core FFE and clock generation circuitry. Comparison with recent mixed-mode receivers shows superior area and power efficiency for the core FFE functionality.
This paper proposes a piecewise linear mathematical model for estimating power losses and power conversion efficiency in switched-inductor power management integrated circuits. By exploiting the parasitic resistance extracted from metal routing wires, vias, pads, and bonding wires as well as devices' on-resistance in the power delivery path, this model provides a time-efficient method useful for the pre-layout design stage. The proposed approach significantly reduces the iteration of circuit design and layout required to achieve optimal power efficiency in PMICs. Additionally, it can accurately predict power loss breakdown in just a few minutes, compared to several weeks or even more spent on post-layout simulation. The results of the proposed model demonstrate a good agreement with that of the simulation program with integrated circuit emphasis (SPICE) simulations and silicon measurements. The silicon prototype is implemented in a 0.18 & micro;m CMOS technology and achieves peak power conversion efficiencies of 95.3% for single-inductor single-output operation and 92% for single-inductor four-output operation.
Conventional analog-to-digital converters (ADCs) suffer from irreversible clipping when input amplitudes exceed their fixed full-scale range. Modulo ADCs address this by folding the input signal prior to quantization; however, stable hardware operation under deep-folding conditions and experimental validation of algorithmic recoverability remain outstanding challenges. This paper presents a calibrated FPGA-based modulo ADC platform in which a finite state machine with multi-bit update control governs folding dynamics, replacing instantaneous comparator-triggered feedback to ensure deterministic and stable operation. A controlled under-compensation calibration strategy converts fold-dependent threshold mismatch and oscillatory instability into a bounded constant residual, enabling reliable folding at high folding depths. The platform achieves a dynamic range expansion exceeding two orders of magnitude while maintaining signal fidelity comparable to that of the standalone ADC. Experimental validation across diverse waveforms confirms robust signal acquisition and demonstrates the practical feasibility of dynamic-range extension using modulo sampling principles.
This paper presents the first circuit-level implementation of a continuous-time bandpass delta-sigma ( Delta Sigma ) modulator featuring a bandpass finite impulse response (BP-FIR) DAC in the feedback path. Targeting RF-sampling receiver architectures for reconfigurable multi-band front-ends, the fourth-order modulator employs an LC-based loop filter operating at a 4 GHz sampling frequency with a 1 GHz center frequency. By combining a single-bit quantizer with a BP-FIR feedback DAC, the architecture effectively suppresses out-of-band quantization noise and minimizes the voltage swing at the loop-filter input. This configuration directly addresses the key practical challenges of single-bit continuous-time Delta Sigma modulators by significantly relaxing the loop filter's linearity requirements and mitigating clock jitter sensitivity, all while avoiding the stringent element-matching bottlenecks of multi-bit designs. Validated through layout-aware transistor-level simulations in 28 nm FD-SOI CMOS, the proposed design achieves an SFDR of 71.5 dB and an SNDR of 63.9 dB over a 20 MHz bandwidth while consuming 23.4 mW from a 1 V supply. Delivering a favorable trade-off between dynamic range, power consumption, and implementation complexity, the proposed design is well suited for integration into next-generation software-defined radio (SDR) systems.
Next-generation LiDAR systems demand unprecedented resolution, requiring wide signal bandwidth and high-density pixel arrays that constrain each pixel circuit to $\leq 0.01$ mm2. This limits the complexity and power available for anti-aliasing filtering in the receiver front-end, even though strong attenuation of interference and alias noise is critical to preserve signal fidelity. Voltage-controlled oscillator (VCO)-based analog-to-digital converters (ADCs) offer inherent anti-aliasing through spectral shaping, but for bandwidths $\geq $ 50 MHz, the attenuation is insufficient, necessitating dedicated analog filters that undermine area and power. To resolve this, we propose a novel sampling technique for VCO-ADCs, employing quadrature clocks instead of conventional clocking. The resulting output spectrum exhibits a quasi- $sinc^{3}$ -shaped response that improves alias attenuation by ~10 dB to 80 dB at 50 MHz bandwidth—the highest reported to date—eliminating the need for analog filters. We derive an analytical expression for this response, accounting for non-idealities and offering insight into the parameters governing the shaping behavior. The technique is demonstrated with a proposed filterless, low-complexity VCO-ADC circuit in CMOS 65 nm, occupying just 0.0017 mm2—43% smaller than the state-of-the-art—and dissipating only 0.42 mW at 2 GHz sampling in simulation. Benchmarking shows a figure-of-merit of 56 fJ/conversion-step, $\sim 1.1\times $ better than the best reported design.
In this paper, we introduce the notion of pseudo-Chebyshev functions over finite fields. In brief, such functions correspond to a generalization of the n-th Chebyshev polynomial, where n is not restricted to integer values, but can take on any rational value. Our approach is mainly based on concepts of trigonometry over finite fields. Besides defining the referred functions, we derive several of their properties and establish necessary and sufficient conditions for them to permute the elements of Fq. Potential applications of the proposed functions are preliminarily discussed.
This article introduces a machine-learning (ML)-driven co-design and optimization framework for open-loop analog linearization of VCO-ADCs, especially operating in the low supply-voltage (VDD) regime, and demonstrated on a new coupled-oscillator-ensemble (COE) circuit architecture. The high-dimensional optimization space associated with the embedded linearization tuning ‘knobs’ of the VCOs renders exhaustive transistor-level search infeasible. To address this challenge, a deep neural network (DNN) surrogate is trained on a compact set of transistor-level transient simulations capturing the COE’s composite voltage-to-frequency ( $V$ -to- $f$ ) characteristics. This surrogate enables rapid exploration of the vast tuning-knob landscape and steers an evolutionary genetic algorithm (GA) toward configurations that optimize harmonic distortion (HD). To further enhance HD-prediction robustness and incorporate VDD variation awareness, the framework integrates advanced ML techniques. Monte Carlo (MC)–perturbed GA optimization improves resilience to parameter uncertainty, while a stacked-ensemble surrogate network, constructed from expert-VDD-specific base models fused with a hybrid encoder-combiner meta-learner, facilitates accurate VDD–aware predictions. The resulting optimized tuning settings are transferred to a Cadence simulation environment for transistor-level verification of the VCO–ADC, achieving a mean third-order harmonic distortion ( $\text {HD}_{3}$ ) of 55 dB. Across a wide 0.4—0.6 V supply range ( $\approx 40\%$ variation), $\text {HD}_{3}$ remains above 50 dB through the DNN’s supply-adaptive dynamic programming of the tuning-knob values.
Memristive devices have attracted significant attention due to their intrinsic nonlinearity, memory-dependent behavior, and ability to encode information through continuously tunable resistive states at the nanoscale. Beyond its use in non-volatile memories and neuromorphic architecture, the memristor is increasingly investigated for chaotic and nonlinear circuit design, where its analog hysteretic response can enable compact and energy-efficient chaotic systems. To date, memristor-based chaotic circuit designs have predominantly focused on binary (abrupt-switching) devices, while analog (gradual-switching) memristors, despite their advantages such as low operating current and high reproducibility, have not yet been explored for their potential to generate and sustain chaotic behavior. In this work, we use a self-rectifying BiFeO3 (BFO) memristor as a demonstrator to investigate how analog nonlinear dynamics can be harnessed for chaotic RC oscillator design. Based on experimental characterization of its frequency-dependent response, a physically grounded behavioral model is developed to accurately capture the device’s analog and self-rectifying characteristics, showing excellent agreement with measured data. Using this model, we adapt a low-frequency third-order RC chaotic circuit from the literature by replacing its diode with the BFO memristor and its parasitic capacitance, where the BFO device serves as the single nonlinear element responsible for chaotic signal generation. More importantly, the circuit parameters must be finely tuned to match the analog nonlinear dynamics of the BFO memristor with the RC network and ensure stable chaotic operation, ultimately yielding a fifth-order memristive oscillator. The proposed circuit exhibits rigorous chaos, as confirmed by Lyapunov exponent analysis, features a double-scroll attractor, and demonstrates a broad parameter range of chaotic behavior verified through bifurcation diagram analysis. This work represents the demonstration of chaos generation by leveraging, for the first time, the analog nonlinear dynamics in a self-rectifying memristor, establishing a direct link between device-level nonlinear dynamics and system-level chaotic behavior, and providing a technology-agnostic framework for the development of low-power, scalable chaotic circuits applicable to diverse applications.
This work introduces a low-power, linear-in-log capacitance sensing circuit tailored for large-area electrowetting-on-dielectric (EWOD) arrays utilizing thin-film transistor (TFT) technology. By leveraging the intrinsic time constants of the circuit, the proposed approach achieves enhanced sensitivity at low capacitance levels, effectively addressing scenarios where the EWOD electrode capacitance is on par with parasitic capacitances present in the system. Fabricated using a $4.5~\mu $ m Low Temperature Polysilicon (LTPS) TFT process, the circuit demonstrates up to 6-bit resolution, corresponding to 63 distinct measured capacitance levels, and measures capacitance variations as small as 61.3 fF. Two circuit variants are presented: the first, employing a one-transistor–one-resistor (1T1R) input stage, which operates at a peak/mean power consumption of $16~\mu $ W / $3.0~\mu $ W and occupies $324\times 324~\mu $ m2; the second, incorporating a current mirror (CM) input stage, consumes $35~\mu $ W / $9.4~\mu $ W with an area of $317\times 506~\mu $ m2. Both implementations mark a significant improvement in resolution, sensitivity and power efficiency compared to the current state-of-the-art in TFT technology.
