Deuterated oxides exhibit prolonged hot carrier lifetimes at room temperature. We report evidence that this improved hot carrier hardness exists over the temperature range between −25 °C and 200 °C. However, the benefit of deuterium incorporation deceases with increasing stress temperature. Furthermore the VT-shift shows a remarkable absence of temperature dependence for the deuterated samples. The results are compared to the existing vibration-relaxation model.

In recent literature, a controversy has arisen over the question whether deuterium improves the stability of the MOS gate dielectric. In particular, the influence of deuterium incorporation on the bulk oxide quality is not clear. In this letter, deuterium or hydrogen is introduced during either the gate oxidation, postoxidation anneal, and/or the postmetal anneal (PMA). The oxide bulk degradation was evaluated using charge-to-breakdown and stress-induced leakage current; and the oxide interface degradation using hot-carrier degradation and low-frequency noise. The obtained results show that the oxide bulk does not benefit from the presence of deuterium, regardless of the stage of deuterium introduction, or the gate oxide thickness. The oxide interface is more stable only when deuterium is introduced in the PMA.

This work presents a wide range of growth rate data of thin (1-60 nm) silicon oxides grown in an ultradiluted ambient of H2O or D2O in the temperature range 750-950 degrees C. A considerable and constant difference of 18% in oxidation rate is found between the two oxidizing species. Modeling of the obtained oxidation data with the Deal-Grove, Reisman, and Wolters models results in poor fits. The extracted activation energy suggests the presence of a rapid initial oxidation regime for the first 10 nm, not incorporated in the investigated models. (c) 2005 The Electrochemical Society.

The gate current in a MOS structure can deform A Cascade probe station and Agilent's 4156C were used for the result of a quasi-static capacitance-voltage measurement. capacitance-voltage measurements. Data were verified with In this paper, several correction methods are presented and the HP 4140B (and no deviations were found). The discussed to compensate for this effect. Limitations of all guidelines for accurate C-Y measurements on the 4156C in methods are quantified and workarounds are proposed. (3,4) were followed where possible.

In recent literature, a controversy has arisen over the question whether deuterium improves the stability of the MOS gate dielectric. It appears as if this controversy finds its origin in the different stages (e.g. oxidation or post metal anneal) deuterium is introduced in the CMOS process. This paper investigates this in detail. The obtained results show that the hot carrier degradation only benefits from an isotope effect when deuterium is introduced in the post metal anneal. At the same time, charge to breakdown for high quality oxides does not benefit from an isotope effect, regardless of the processing stage deuterium is introduced, or the gate oxide thickness used. This is verified on two different sets of wafers fabricated in two different laboratories.

In recent literature, a controversy has arisen over the question whether deuterium improves the stability of the MOS gate dielectric. This work presents a wide range of growth rate data of H2O and D2O gate oxides in an ultra-diluted ambient. A considerable and constant difference in oxidation rate is found between the two species. Although literature suggests a correlation between growth rate and dielectric quality, the degradation measurements on MOS capacitors with 8.5 nm gate oxides grown at 950 °C at low partial pressure show only a very weak difference between the isotopes. It appears that the difference in oxidation rate does not affect the gate oxide quality, and high quality grown gate oxides do not appear to benefit from the deuterium isotope effect.

A study of the chemical mechanical polishing (CMP) of thin copper films using fixed-abrasive pads is presented. The composition of the polishing solution is optimized by investigating the impact of both the oxidizer concentration and the pH of the solution on the polishing characteristics of copper. The resulting optimum polishing solution gives a high removal rate (>300 nm/min), good uniformity (standard deviation 3%) and a very high selectivity for the oxide removal rate (>100:1). The dependence of the removal rate of copper on the geometry is studied for different feature sizes and various pattern densities. The geometry dependency is considerably less in the slurry-free process than in the conventional slurry CMP. This is crucial for copper CMP because it helps to minimize the overpolishing time and consequently the amount of dishing. Damascene copper structures have been successfully made by polishing patterned test wafers. The amount of dishing of the copper lines is smaller than that for the conventional polishing technique. The polished wafers were easily cleaned; a standard rinsing step seemed to be sufficient.

Periodically switching the MOSFET 'off' (switched biasing), is known to reduce the low-frequency (LF) noise power spectrum. In this work, the constant and switched biased LF noise has been measured on devices before and after hot-carrier stress. The switched biased LF noise is more sensitive to hot-carrier degradation than the constant biased LF noise. The anomalous noise reduction, due to switched biasing, observed for fresh devices, gradually disappears as the devices are subjected to hot-carrier stress. Devices with a deuterium passivated SiO2/Si interface degrade significantly slower, as seen from our LF noise measurements.

The gate current in a MOS structure can deform the result of a quasi-static capacitance-voltage measurement. In this paper, several correction methods are presented and discussed to compensate for this effect. Limitations of all methods are quantified and workarounds are proposed.