This work presents a novel Field Programmable Gate Array (FPGA)-based architecture for encrypting telemetry together with high-definition video data in unmanned aerial vehicles (UAVs). The design uses the Advanced Encryption Standard (AES-128) to secure data and video streams, ensuring protection against cyberattacks. The proposed system integrates a pipeline data path for video and telemetry data, coupled with FIFO buffers, enabling efficient handling of different bandwidth requirements while maintaining high throughput. Our platform encrypts/decrypts both down-stream and up-stream telemetry data and encrypts down-stream of video data. To the best of our knowledge, no such architecture has been proposed in the literature, as existing research focus on encrypting only a part of the aforementioned types of data. Experimental results demonstrate that the proposed architecture performs efficiently without adding serious execution delays comparing to existing FPGA platforms, while keeping energy consumption low.

Applications concerning unmanned aerial vehicles (UAVs) have increased in recent years, mainly due to simple configuration, user-friendly navigation, and small weight and size. They are utilized and adopted within many contexts and services, such as mapping, construction inspection and surveillance, and search and rescue (SAR), changing the business perspective. Among different types of UAVs, multicopters or rotary-wing aircraft are the most popular, based on their vertical take-off and landing (VTOL) abilities, maneuverability, low cost, and easy deployment. Although there are many multicopter models available on the market, the prospect of building a custom one is becoming increasingly attractive since there is a variety of electronic parts to choose from. However, given that certain operations require special equipment for the effective operation of the UAV, the selection of the appropriate hardware parts is not an easy task. In this paper, a survey is presented concerning multicopter basic parts. For these parts, the most important methods are presented for calculating critical parameters in order for the total system to operate efficiently according to requirements. Finally, for critical application areas, a set of basic components is suggested for the multicopters’ efficient usage.

Unmanned Aerial Vehicles (UAVs) are used in a wide range of applications. However, since they are vulnerable to cyberattacks security protocols for their data are used. Common existing approaches for data encryption/decryption are based on commercial software platforms which execute their tasks with latency and consume a lot of energy. Moreover, they focus mostly on encrypting/decrypting telemetry data. This paper proposes a Field Programming Gate Array (FPGA)-based architecture for encrypting/decrypting all data exchanged between UAVs and their Ground Station (GS). This architecture uses the Advanced Encryption Standard (AES), known for its robustness, to enhance the confidentiality, integrity, and security. Experimental results show that the proposed architecture performs faster than implementations on well-known software platforms while it consumes less power.

Abstract: Unmanned Aerial Vehicles (UAVs) have a history of over a century of deployment, but in recent decades, they have progressed at a staggering rate. Nowadays, UAVs are used by a large number of civil and military applications. The communication functionality of a UAV with external systems for control and charging is strongly connected with evolving technologies and services. This leads to an increased number of alternatives when designing UAV communications. This review presents the information needed for choosing an efficient communication system between UAVs and two important elements, the Ground Control Station (GCS) and the Charging Station (CS). GCS is responsible for monitoring and controlling the UAV’s units, while CS is used for the formal charging of the UAV. This study aimed at collecting, classifying, and evaluating all of the necessary information in order to obtain the final decision about the kind of communication that is most efficient for a target UAV application. The features of the telemetry open-source protocols are presented for the UAV-GCS communication and evaluated according to the needs of the most significant application domains. Communication between UAVs and CSs is classified depending on the existence of an intermediate server and analyzed considering telemetry protocols and application domains. Communication algorithms are evaluated in terms of time and energy efficiency. Lastly, for the most significant application domains, the most suitable algorithms are matched.

Two-pattern tests target the detection of common failure mechanisms in CMOS VLSI circuits, modelled as stuck-open or delay faults. In this paper, a Reduced-overhead Accumulator-Based BIST scheme for Two-pattern generation (RABIT) is presented, that generates an exhaustive n-bit two-pattern test. RABIT is implemented in hardware utilizing an accumulator whose inputs are driven by a binary counter. An important advantage of the presented scheme is that it can be implemented by augmenting existing data path components, rather than building a new pattern generation structure. Furthermore, with the proposed scheme, the requirement for additional (i.e. control and/or accompanying) circuitry is eliminated. Comparisons with previously proposed schemes reveal that the proposed here scheme presents lower hardware overhead for the implementation of the BIST structure.

The use of Unmanned Aerial Vehicles (UAVs) is growing at a fast pace, as they tend to play an important role in areas such as surveillance, delivery of goods, etc. Τhis is mainly based on their ability to perform flights at low cost with fast deployment. Moreover, they can transmit data produced by embedded sensors and carry packages of different size and weight. Based on these characteristics, the approach of building custom UAVs, for different applications is very common. Since each application requires specific hardware for the UAVs’ efficient operation, the selection of the appropriate parts is not an easy task. In this paper, all the necessary information of the basic UAV hardware parts is presented. Using this information, an approach is suggested, for selecting the most suited hardware parts for the most common application domains.

Nowadays the use of drones in daily life is becoming more and more frequent. One important service of drones is object detection which is used in surveillance and search-and-rescue missions. High performance is a critical requirement for object detection, since drones travel at high flying speeds. Current systems mainly use software platforms which have limited performance. In this paper a hardware architecture is presented for object detection in drones. The ability of the proposed architecture to exploit parallelization in object detection tasks more efficiently than in software platforms, offers lower execution time and more accurate and faster results. The proposed architecture is implemented using an FPGA platform. Experimental results show the benefits of this architecture compared to a software platform in terms of performance and detection-precision.

One of the most important sections on UAV technologies is the telemetry communication. Due to the growing needs of UAV applications a number of telemetry protocols are available. Different telemetry protocols can be used in several applications. In this paper we adduce the most important open-source telemetry protocols and their main features. For the most critical UAV application domains we present the most significant telemetry protocols and their characteristics. Afterwards, we compare and classify the telemetry protocols, depending the needs of the UAV application domains. Finally, we propose the most suitable telemetry protocol for each UAV application domain.

UAV applications are starting to increase nowadays. Their data demanding applications are implemented mostly using software platforms. These applications have critical requirements on high performance, power consumption and there should be security at their transmissions, especially for video data. In this paper, an architecture is proposed for secure video transmission for UAV applications. The system consists of a digital camera a transmission board to transmit the video and a FPGA for implementing the security encryption tasks. The camera sends the video data to the FPGA and the inside circuit encrypts the video data. The transmission module transmits the encrypted data to the Ground Station (GS). Measurements taken concerning the execution time and power consumption, reveal the benefits of the proposed architecture in comparison with well-known software platforms.

In modern and rapidly evolving society, as you drones are not only a means of entertainment but also a tool that we use in a variety of applications, such as precision farming, aerial photography and video, mapping, parcel transportations, search and rescue and in many other applications. In order for these applications to be successful, drones must constantly evolve, in terms of the autonomy of their flights, but also in the management of the energy they consume, in order to be able to travel long distances. Electric drones mostly use lithium polymer batteries (LiPo) for their power supply and their flight time depends on their battery capacity and is directly affected by its weight and ranges from 5 to 45 minutes with a full charge of its batteries. According to these time constraints the distances at which a drone can operate autonomously is narrow. In recent years, scientists, research teams and universities have developed drone charging systems that do not require human intervention. This paper presents a survey of drone charging stations that can be used in a variety of applications. The survey covers charging stations that use wired and wireless power transfer (WPT) methods, and compares their main elements and features.

UAV applications are providing an extended range of services in society's needs. These applications require high execution speed and security to all transmitted data. In this paper an architecture is proposed for secure UAV applications. The architecture consists of a microcontroller to execute the flight controller tasks and a FPGA for implementing the security related tasks. The microcontroller is an Arduino which is widely used in UAVs. Arduino communicates with all sensors and generates outputs needed for controlling the UAV's motors. The circuit inside the FPGA encrypts/decrypts data related to transmission. Measurements taken concerning the execution time and power consumption, reveal the benefits of the extra hardware added for encryption/decryption in comparison with those of a single microcontroller.

Many experimental hardware Trojans explore the potential threat vectors. However, if a Trojan largely affects area, power or operating speed, then it can be easy to detect. We explore the cost in area, power and operating speed of two small, focused attacks on the Parwan processor implemented with a standard cell library. The resulting cost in total area varied from a 0.05% to a 0.09% increase in the area of the design and similar results in the power consumption, while no delay overhead was imposed.

Built-in self test (BIST) techniques use test pattern-generation and response-verification operations, reducing the need for external testing. BIST techniques that use arithmetic modules existing in the circuit (accumulators, counters etc.) to perform the test-generation and response-verification operations have been proposed in the open literature. Two-pattern tests are exercised to detect complementary metal oxide semiconductor (CMOS) stuck-open faults and to assure correct temporal circuit operation at clock speed (delay fault testing). In this study, a novel, arithmetic module-based BIST architecture for two-pattern testing (ABAS) is presented that exercises arithmetic modules to generate two-pattern tests; the hardware overhead required by the presented scheme, provided the availability of such modules is by far the lowest of all schemes that have been presented for the same purpose in the open literature.

Built-In Self Test (BIST) techniques perform test pattern generation and response verification operations on-chip. In Arithmetic BIST, modules that commonly exist in datapaths (accumulators, counters, etc.) are utilized to perform the above-mentioned operations. In order to detect faults that occur into current CMOS circuits, two-pattern tests are required. Furthermore, delay testing, commonly used to assure correct temporal circuit operation at clock speed requires two-pattern tests. In this paper a novel two-pattern test generator for Arithmetic BIST is presented. Its hardware implementation compares favorably to the techniques that have been presented in the literature. Application of the proposed scheme for the two-pattern testing of ROM modules revealed that the testing of small-to-medium size ROMs is completed within reasonable time and with negligible hardware overhead.

The IEEE P1619 standard for achieving high degree of security in shared storage media is explored, in terms of area requirements, performance and resource exploitation. Several architectures are considered, highlighting the potentials of the achieved throughput, selecting the appropriate architecture. The results are interesting: a) for consumer electronics vendors, offering competitive architectures for low-cost technologies, and b) for consumers requiring secure and highly performing (in terms of encryption) storage devices.

The IEEE P1619 standard for achieving high degree of security in shared storage media is explored, in terms of area requirements, performance and resource exploitation. Several architectures are considered, highlighting the potentials of the achieved throughput, selecting the appropriate architecture. The results are interesting: a) for consumer electronics vendors, offering competitive architectures for low-cost technologies, and b) for consumers requiring secure and highly performing (in terms of encryption) storage devices.

A comparison of two novel P1619 XTS-AES architectures, is presented in this paper. Two of the architectures are introduced for the first time and are aiming in either cost- or performance-efficient operation. The implementations are based on the use of a single or dual AES cores for simultaneous Tweak value calculation and block encoding/decoding operations.

We present an architecture of decoupled processors with a memory hierarchy consisting only of scratch-pad memories, and a main memory. This architecture exploits the more efficient pre-fetching of Decoupled processors, that make use of the parallelism between address computation and application data processing, which mainly exists in streaming applications. This benefit combined with the ability of scratch-pad memories to store data with no conflict misses and low energy per access contributes significantly for increasing the system's performance. The application code is split in two parallel programs the first runs on the Access processor and computes the addresses of the data in the memory hierarchy. The second processes the application data and runs on the Execute processor, a processor with a limited address space--just the register file addresses. Each transfer of any block in the memory hierarchy up to the Execute processor's register file is controlled by the Access processor and the DMA units. This strongly differentiates this architecture from traditional uniprocessors and existing decoupled processors with cache memory hierarchies. The architecture is compared in performance with uniprocessor architectures with (a) scratch-pad and (b) cache memory hierarchies and (c) the existing decoupled architectures, showing its higher normalized performance. The reason for this gain is the efficiency of data transferring that the scratch-pad memory hierarchy provides combined with the ability of the Decoupled processors to eliminate memory latency using memory management techniques for transferring data instead of fixed prefetching methods. Experimental results show that the performance is increased up to almost 2 times compared to uniprocessor architectures with scratch-pad and up to 3.7 times compared to the ones with cache. The proposed architecture achieves the above performance without having penalties in energy delay product costs.

Many cryptographic primitives that are used in cryptographic schemes and security protocols such as SET, PKI, IPSec, and VPNs utilize hash functions, which form a special family of cryptographic algorithms. Applications that use these security schemes are becoming very popular as time goes by and this means that some of these applications call for higher throughput either due to their rapid acceptance by the market or due to their nature. In this work, a new methodology is presented for achieving high operating frequency and throughput for the implementations of all widely used—and those expected to be used in the near future—hash functions such as MD-5, SHA-1, RIPEMD (all versions), SHA-256, SHA-384, SHA-512, and so forth. In the proposed methodology, five different techniques have been developed and combined with the finest way so as to achieve the maximum performance. Compared to conventional pipelined implementations of hash functions (in FPGAs), the proposed methodology can lead even to a 160 percent throughput increase.

Current embedded systems are usually designed for data-dominated applications, but they have a tight energy and time budget. Scratch-pad memories are completely software-controlled memories with predictable behaviour and good performance and energy characteristics, thus they tend to become a standard feature in many embedded systems. However, their predictability is not helping if the application accesses its data dynamically, when the addresses of the accessed data depend on the application's input. In such cases, predetermining the scratch-pad content at design-time is not always possible as the compiler cannot predict the runtime input. Moreover, in this case, both data reuse and data placement in the scratch-pad are inefficient because chunks of data already stored cannot be efficently reused and combined with the runtime accessed data blocks. State-of-the art techniques copy each new data block to the scratch-pad without considering whether portions of them are already in it. Such dynamic temporal locality cannot be predicted or exploited by the compiler. The authors here present a system architecture, strongly connected to the system's scratch-pad and the processor's compiler, which is able to efficiently exploit run-time data reuse in the scratch-pad by being capable of holding valuable information, such as the exact data contents of the scratch-pad at runtime, and using it to do all the necessary operations for placing each new data block in scratch-pad. It is. ne tuned for applications with run-time reuse between rectangular data blocks. The application domain of the proposed architecture is multimedia applications with run-time reuse, certain applications with linked lists and multi-threaded applications. It operates in a time and energy-efficient manner when compared with existing scratch-pad architectures without the authors' scratch-pad accelerator engine, showing its higher normalised performance and lower normalised energy consumption. Experimental results show up to 2.5 times performance increase compared with existing scratch-pad architectures and 5 times compared with cache architectures and energy decrease up to 1.9 and 3.9 times, respectively.