To meet the performance requirements of highly data-centric applications (e.g. edge-AI or lattice-based cryptography), Computational SRAM (C-SRAM), a new type of computational memory, was designed as a key element of an emerging computing paradigm called near-memory computing. For this particular type of applications, C-SRAM has been specialized to perform low-latency vector operations in order to limit energy-intensive data transfers with the processor or dedicated processing units. This paper presents a design methodology that aims at making the C-SRAM design flow as simple as possible by automating the configuration of the memory part (e.g. number of SRAM cuts and access ports) according to system constraints (e.g. instruction frequency or memory capacity) and off-the-shelf SRAM compilers. In order to fairly quantify the benefits of the proposed memory selector, it has been evaluated with three different CMOS process technologies from two different foundries. The results show that this memory selection methodology makes it possible to determine the best memory configuration whatever the CMOS process technology and the trade-off between area and power consumption. Furthermore, we also show how this methodology could be used to efficiently assess the level of design optimization of available SRAM compilers in a targeted CMOS process technology.

Supercomputers will soon achieve Exascale-level computing performances mainly thanks to the introduction of innovative hardware technologies around the processors. This article explains architectural and performance evolutions and describes how 3D integration technologies have allowed heterogeneity and increased bandwidth that are decisive for hardware innovations contributing to Exascale.

In the context of high performance computing (HPC), energy efficiency and computing density are key for targeting exascale architectures. Close integration of chiplets, active interposer and field programmable gate arrays (FPGA) paves the way for dense, efficient and modular compute nodes. In this paper, we detail the ExaNoDe multi-chip-module (MCM) combining the integration of a substrate, an active interposer, some chiplets and bare dice. The reported MCM demonstrates that the multi-level integration flow enables tight integration of hardware accelerators in a heterogeneous HPC compute node.