Interposer-based multi-die FPGAs (2.5D) are composed of multiple dies interconnected externally via wires, allowing the creation of FPGA systems with increased capacity. These external connections are generally fewer than the die's internal interconnection network and contribute to a higher delay and wirelength. These architectural limitations must be considered while optimizing PnR tools for multi-die solutions. The configuration of the interposer interface plays a crucial role in determining the routing resource availability at the die boundary and in ensuring congestion-free solutions. Interposer wires are generally designed to be thicker than the wires in the die's internal interconnection network, and their length can significantly impact overall delay. Longer interposer wires allow longer strides across the die, reducing the need for additional internal routing resources to handle cross-die net routing. Given these conflicting factors, it is crucial to determine an optimal length for the interposer wires. In this study, we aim to investigate how the length of the interposer wire influences the overall performance of PnR tools. We have developed a multi-die placer, LiquidMD and router, CRouteMD capable of accommodating various interposer lengths and have analyzed the impact of interposer length on the quality of PnR. Using a flexible interposer interface based on Xilinx's Virtex-7 architecture, we investigated wire lengths ranging from L12 to L48. In our comparison of PnR results across various interposer wire lengths, ranging from L12 to L48, we found that an optimal interposer wire length of approximately 14% of the die height (L30) improves the overall routing performance. This length of interposer wire reduces the CPD by 5% as compared to the longest interposer wire length which covers 22% of the die height.
Clustering is a critical step in VLSI design. Good clusters can aid in partitioning, floorplanning, and netlist reduction. In this work, we adopt a data mining technique to extract modular clusters and networks between clusters from placement evolution. We observe that state-of-the-art analytical placers propagate standard cells as Modular Clusters during placement evolution. And other noisy cells, which cannot be assigned to a specific cluster, form a network structure called Inter-Cluster Networks (ICNs). We propose Cascade HDBSCAN to extract Modular Clusters at different granularity as well as Inter-Cluster Networks in placement evolution. And we reveal Modular Clusters and Inter-Cluster Networks adhere to different Rent's rules. Furthermore, we provide a detailed analysis on the clustering structure and demonstrate VLSI netlists are small-world networks. Modular Clusters are localized groupings connected by Inter-Cluster Networks that function as shortcuts in the networks.
Moore's Law has been guiding the development of the VLSI industry for the past half-century. This law underscores fabrication technology's crucial role in enhancing chip performance. However, with technology nearing physical limitations, we envisage that there is still significant potential for optimizing interconnection complexity in VLSI design. Interconnection complexity is characterized by Rent's Rule and the Rent exponent. We propose a new recursive normalized approach that can measure the Rent exponent accurately by eliminating the imbalance between blocks of different sizes. Then we demonstrate that optimizing the Rent exponent of the FPGA netlist can yield substantial benefits throughout the CAD flow process, particularly in physical design. By employing the GNL synthetic netlist generator to control interconnection complexity, we observe that a lower Rent exponent results in reduced running time, total wirelength and area usage. We also include real-world circuits from the Koios 2.0 benchmark suite in our analysis. The run-time of packing, placement and routing are ranging from exponential to double-exponential with respect to the Rent exponent. Our study highlights the significant impact of interconnection complexity on the EDA physical design flow. The results suggest that optimizing the netlist's interconnection structure during logic synthesis or packing to reduce complexity could enhance the efficiency and performance of the EDA flow.
Electronic Design Automation (EDA) for Field Programmable Gate Arrays (FPGAs) strives to optimize the timing properties of physical circuits on FPGAs. The process involves logic synthesis and packing in physical synthesis, which generates a circuit graph. This graph is subsequently placed and routed onto the FPGA architecture to create a physical circuit. Researchers have demonstrated that merely minimizing circuit size does not necessarily lead to an optimal wirelength. Namely, as circuit size decreases the interconnection complexity can (and normally does) increase. This work focuses on gaining a better understanding of this phenomenon. We investigate the trade-off between size and interconnection complexity by examining ideal circuit graphs which are an abstraction of real circuits graphs based on Rent's rule. An ideal circuit is reduced to only three parameters: size Bc, interconnection complexity r and terminals per block K. First we study the effect of size Bc and interconnection complexity r on wirelength by making a visual representation with Donath's wirelength prediction method. The created visual clearly exposes and provides insight in the tradeoff between size and interconnection complexity. Furthermore, it shows that interconnection complexity is limited subject to circuit size. Second, we derive the shape of ideal circuit graphs based on its three parameters. We use the hypervolume-hyperarea interpretation of Rent's rule as a basis for constructing ideal circuit graphs. In understanding the structure of ideal circuit graphs it becomes clear why complexity is bound by size. We find that the complexity r of an ideal circuit is lower than log3(Bc)−1/log3(Bc). The model for building ideal circuit graphs enhances our intuitive understanding of interconnection structure in FPGA circuits and might be the basis for a new synthetic benchmark generation technique.
Interposer-based multi-die FPGAs comprise multiple dies interconnected externally via wires, enabling the creation of FPGA systems with greater capacity. These external connections are fewer in number than the internal interconnection network of a die and they also contribute to increased delay and wirelength. These architectural shifts necessitate placement and routing tools to strategically reduce the count of signals at the die boundary. Multi-die FPGA systems also offer substantial potential for design modularity, where each die can be optimized for specific functionalities. Adapting EDA tools to leverage these inherent device characteristics is imperative. Additionally, the modular nature of the system paves the way for parallelized implementations. Previous studies on multi-die FPGA placement have primarily concentrated on reducing signal crossings across die boundaries via global optimization. This strategy, however, incurs significant runtime demands, as it treats the multi-die FPGA as a unified fabric. This study presents a new methodology to partition and parallelize placement within a multi-die architecture. Our approach facilitates the optimization of partitioned nets without the reliance on a global optimization step. With netlist partitioning and adding virtual anchor blocks, the subcircuits can be placed on each die in parallel. The multi-die placer algorithm is integrated into the fast analytical placement tool 'Liquid'. A comprehensive performance comparison of our multi-die placer with the single-die monolithic implementation unveils similar quality results with improved runtime efficiency. Lastly, we compare our strategy to the widely-used academic placer, VPR, which relies on global optimization. The results demonstrate a 42x enhancement in runtime for lower estimations of Total Wire-length (TWL) and Critical Path Delay (CPD).
Design rule violation (DRV) is one of the significant challenges in designing integrated circuits. To successfully manufacture a chip, it is crucial to create a DRV clean layout. However, as technology nodes shrink and the cell density of the design increases, design rules have become increasingly difficult to meet, making the routing more complex. In addition, the conventional design flow has a problem in that it primarily determines design parameters and tool options, while evaluating routability at the end of the design flow. Furthermore, due to complex design rules, even global routers are not accurate enough, so routability can be assessed after actual routing, leading to significantly extended design turn-around times. In this paper, we introduce a framework that leverages machine learning techniques to overcome the limitations of the conventional design flows. We also present the challenges that arise during the construction of the framework, along with related research. Furthermore, we discuss issues that remain unresolved.
Design Technology Co-optimization (DTCO) and System Technology Co-optimization (STCO) have become essential techniques to sustain Moore's law, while the geometric scaling has slowed down in the last decade. With new technology nodes are on the horizon, the anticipated scaling boost faces a potential hindrance known as the "pin density wall". This challenge arises from the shrinking cell area and the intricate 3D structure of advanced technology nodes, which limits the options for pin accessibility. Consequently, the advantages of cell area shrinkage in given existing advanced architectures may not translate well to block-level design. To address this issue, additional design methodologies regarding routability need to be explored. In this work, we will describe the scope and potential benefits of different design knobs for standard cell design, device architectures, and block-level placement and route. In addition, we will cover the challenges and future research directions by investigating physical space constraints, cell design automation flow, and existing design tool limitations.
With advances in lithography technology, the minimum metal pitch (MP) becomes smaller than the contacted poly pitch (CPP). This difference has long prompted the need to seek an optimal ratio between CPP and MP. Automated cell synthesis with conditional design rules offers a valuable lever to speed up the technology exploration process and to identify the best "gear ratio" (GR) for Design-Technology Co-optimization (DTCO) exploration. Existing approaches for cell layout generation frameworks have primarily supported uniform grids with limited gear ratio options. In this work, we present SMTCell, a new exploratory framework for cell layout generation that allows flexible gear ratio options using a graph-based data structure. We employ distance-based objective functions and conditional design rule parameters to adapt to varying pitch values. This approach enables us to investigate and discover optimal layouts under diverse technology node settings. An acceleration feature drastically trims the solution space, resulting in a speed increase of up to 19X without sacrificing the quality of the original solutions. With SMTCell, cell synthesis automation can be configured to accommodate a wide range of design choices. We conduct an empirical study to assess the impact of gear ratio at block-level synthesis, place and route (SP&R) outcomes, with the ultimate goal of identifying the most effective technology and standard cell configurations in terms of design power, performance and area (PPA) metrics.
Network-on-chips (NoCs) are envisioned to be a scalable communication substrate for Network-on-Memory (NoM) architectures. However, modern data-intensive workloads continue to overwhelm the NoC link capacity, dramatically increasing memory service latency and causing a great performance loss. We introduce DECORAM, a data (de-)/compression scheme implemented within a DRAM-based NoM architecture. DECORAM uses a lookup table (LUT) to store compressed codes of common data patterns, and exploits this LUT during LLC misses to transmit these codes via NoC, instead of the original uncompressed data. We formulate compression and decompression mechanisms as a combination of LUT-based pattern matching and prefix concatenation, which are implemented using low-latency DRAM row activations and exploiting analog properties of the DRAM cell. To support DECORAM, we introduce a minimal design change of adding isolation transistors in a subarray to activate inter-subarray data movement based on the content of its row buffer. Our DECORAM controller reduces the compression and decompression latency by exploiting subarray-level parallelism to compress/decompress several CPU data misses, simultaneously. We evaluate DECORAM using data-intensive workloads from SPEC, APACHE, PARSEC, and in-memory computing benchmark suites. Our results show that compared to a baseline NoM, DECORAM significantly improves performance (average 30%) and energy (average 32%). Compared to a conventional NoC compression mechanism, DECORAM reduces memory area by 27% and energy by 12%, while delivering 7% higher performance improvement.
High-capacity multi-die FPGA systems generally consist of multiple dies connected by external interposer lines. These external connections are limited in number. Further, these connections also contribute to a higher delay as compared to the internal network on a monolithic FPGA and should therefore be sparsely used. These architectural changes compel the placement & routing tools to minimize the number of signals at the die boundary. Incorporating a netlist partitioning step in the CAD flow can help to minimize the overall number of signals using the cross-die connections. Conventional partitioning techniques focus on minimizing the cut edges at the cost of generating unequal-sized partitions. Such highly unbalanced partitions can affect the overall placement & routing quality by causing congestion on the denser die. Moreover, this can also negatively impact the overall runtime of the placement & routing tools as well as the FPGA resource utilization. In previous studies, a low value of the unbalance was proposed to generate equal-sized partitions. In this work, we investigate the factors that influence the netlist partitioning quality for a multi-die FPGA system. A die-level partitioning step, performed using hMETIS, is incorporated into the flow before the packing step. Large heterogeneous circuits from the Koios benchmark suite are used to analyze the partitioning-packing results. Consequently, we examine the variation in output unbalance, the number of cut edges vs the input value of unbalance. We propose an empirical optimal parametric value of the unbalance factor for achieving the desired partitioning quality for the Koios benchmark suite.
To meet the performance requirements of highly data-centric applications (e.g. edge-AI or lattice-based cryptography), Computational SRAM (C-SRAM), a new type of computational memory, was designed as a key element of an emerging computing paradigm called near-memory computing. For this particular type of applications, C-SRAM has been specialized to perform low-latency vector operations in order to limit energy-intensive data transfers with the processor or dedicated processing units. This paper presents a design methodology that aims at making the C-SRAM design flow as simple as possible by automating the configuration of the memory part (e.g. number of SRAM cuts and access ports) according to system constraints (e.g. instruction frequency or memory capacity) and off-the-shelf SRAM compilers. In order to fairly quantify the benefits of the proposed memory selector, it has been evaluated with three different CMOS process technologies from two different foundries. The results show that this memory selection methodology makes it possible to determine the best memory configuration whatever the CMOS process technology and the trade-off between area and power consumption. Furthermore, we also show how this methodology could be used to efficiently assess the level of design optimization of available SRAM compilers in a targeted CMOS process technology.
Many commercial FPGA placement tools are based on the SimPL framework where the Lower Bound (LB) phase optimizes wire length and timing without considering cell overlaps and the Upper Bound (UB) phase spreads out cells while considering the target FPGA architectures. In the SimPL framework, the number of iterations depends on design complexity and the quality of UB placement, which highly impacts runtime. In this work, we propose a machine learning (ML) scheme where the anchor weights of cells are dynamically adjusted to make the process converge in a pre-determined budget for the number of iterations. In our approach and for a given FPGA architecture, a ML model constructs a trajectory guide function that is used for adjusting anchor weights during SimPL's iterations. Our experimental results on industrial benchmarks show, we can achieve on average 28.01% and 4.7% runtime reduction in the runtime of Global Placement and the runtime of the whole placer, respectively while maintaining the quality of solutions within an acceptable range.
Accurate delay prediction is important in the early stages of logic and high-level synthesis. In technology mapping for field programmable gate array (FPGA), a gate-level circuit is transcribed into a lookup table (LUT)-level circuit. Quick timing analysis is necessary on a pre-mapped circuit to guide optimizations downstream. However, a static timing analyzer is too slow due to its complexity and highly inaccurate like other faster empirical heuristics before technology mapping. In this work, we present a machine learning based framework for accurately and efficiently estimating the delay of a gate-level circuit from predicting the depth of the corresponding LUT logic after technology mapping. Our experimental results show that the proposed method achieves a 56x accuracy improvement compared to the existing delay estimation heuristic. Instead of running the mapper for the ground truth, our delay estimator saves 87.5% on runtime with negligible error.
Technology node scaling is driven by the need to increase system performance, but it also leads to a significant power integrity bottleneck, due to the associated back-end-of-line (BEOL) scaling. Power integrity degradation induced by on-chip Power Delivery Network (PDN) IR drop is a result of increased power density and number of metal layers in the BEOL and their resistivity. Meanwhile, signal routing limits the SoC performance improvements due to increased routing congestion and delays. To conquer these issues, we introduce a disruptive technology: wafer backside (BS) connection to realize chip BS PDN (BSPDN) and BS signal routing. We first provide some key wafer processes features that were developed at imec to enable this technology. Further, we show benefits of this technology by demonstrating a large improvement in chip power integrity and performance after applying this technology to BSPDN and BS routing with a sub-2nm technology node design rule. Challenges and outlook of the BS technology are also discussed before conclusion of this paper.
Identifying nets in a placement which will be very likely to be detoured routes in routing is very useful in that (1) in conjunction with the routing congestion, path timing, or design rule violation (DRV) prediction, predicting detour nets can be used as a complementary means of characterizing the outcome of those predictions in a more depth and (2) we can place more importance on the detour predicted nets for optimizing timing and routing resources in the early stage of placement since those nets consume more timing budget as well as metal/via resources. In this context, this work proposes a neural network based detour net prediction model. Our proposed model consists of two parts: CNN based and ANN based. The CNN based model processes the features describing various physical proximity maps or states while the ANN based model processes the features of individual nets in the form of vector descriptions, concatenated to the CNN outputs. Through experiments, we analyze and assess the accuracy of our prediction model in terms of F1 score and the complementary role of timing prediction and optimization. More specifically, it is shown that our proposed model improves the prediction accuracy by 9.9% on average in comparison with that produced by the conventional (vanilla ANN based) detour net prediction model. Furthermore, linking our prediction model to a state-of-the-art timing optimization of the commercial tool is able to reduce the worst negative slack by 18.4%, the total negative slack by 40.8%, and the number of timing violation paths by 30.9% on average.
Current technology trend of VLSI chips includes sub-10 nm nodes and 3D ICs. Unfortunately, due to significantly increased Joule heating in these technologies, interconnect reliability has become a significant casualty. In this paper, we explore how interconnect power dissipation (of CV 2 /2 per logic transition) and thus heating can be effectively constrained during a power-optimizing physical synthesis (PS) flow that applies three different PS transformations: cell sizing, Vth assignment and cell replication; the latter is particularly useful for limiting interconnect heating. Other constraints considered are timing, slew and cell fanout load. To address this multi-constraint power-optimization problem effectively, we consider the application of the aforementioned three transforms simultaneously (as opposed to sequentially in some order) as well as simultaneously across all cells of the circuit using a novel discrete optimization technique called discretized network flow (DNF). We applied our algorithm to ISPD-13 benchmark circuits: the ISPD-13 competition was for power optimization for cell-sizing and Vth assignment transforms under timing, slew and cell fanout load constraints; to these we added the interconnect heating constraint and the cell replication transform---a much harder transform to engineer in a simultaneous-consideration framework than the other two. Results show the significant efficacy of our techniques.
Close integration of control electronics with 3D assembly of photonics and CMOS opens the way to highperformance computing architectures partitioned in chiplets connected by optical NoC on silicon photonic interposers. In this talk, we give an overview of our works on optical links and NoC for manycore systems. We leverage the POPSTAR optical NoC topology and architecture to design a 4-chiplet man...
In this paper we report the design of 3 × 3 wireless routers, based on transmitting and receiving integrated Optical Phased Arrays (OPAs), which allow on-chip optical wireless interconnections. The proposed device aims at achieving reconfigurable wideband optical links between multiple nodes. The general design criteria of these routers are illustrated and performance analysis in terms of insertion loss and crosstalk for different link configurations are reported.
Application Mapping in Network-on-Chip (NoC) design is considered a vital challenge because of its NP-hard nature. Many efforts are made to address the application mapping problem, but none has satisfied all the requirements. For example, Integer Linear Programming (ILP) has achieved the best possible solution but lacks scalability. Advancements in Machine Learning (ML) have added new dimensions in solving the application mapping problem. This paper proposes RAMAN: Reinforcement Learning (RL) inspired algorithm for mapping applications onto mesh NoC. RAMAN is a modified Q-Learning technique inspired by RL, aiming to achieve the minimum communication cost for the application mapping problem. The results of RAMAN demonstrated that RL has enormous potential to solve application mapping problem without much complexity and computational cost. RAMAN has achieved the communication cost within the 6% of the optimal cost determined by ILP. Considering the computational overheads and complexity, the results of RAMAN are encouraging. Future work will improve RAMAN's performance and provide a new aspect to solve the application mapping problem.
The Open Domain-Specific Architecture (ODSA) is a sub-project within the Open Compute project that aims to enable the easy development of chiplet-based designs for domainspecific accelerators. The ODSA aims to define an open physical and logical die-to-die interface, develop chiplet prototypes and establish open workflows for chiplet-based products to ultimately enable a chiplet marketplace. Produ...
